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Chapter 01 Assembly Language

The document provides an overview of assembly language, including its syntax, structure, and the SimpleRisc Instruction Set Architecture (ISA). It explains the role of assemblers, the organization of memory, data types, and different addressing modes. Additionally, it discusses the storage of data and arrays in memory, as well as the structure of assembly statements and types of instructions.
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0% found this document useful (0 votes)
11 views28 pages

Chapter 01 Assembly Language

The document provides an overview of assembly language, including its syntax, structure, and the SimpleRisc Instruction Set Architecture (ISA). It explains the role of assemblers, the organization of memory, data types, and different addressing modes. Additionally, it discusses the storage of data and arrays in memory, as well as the structure of assembly statements and types of instructions.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Computer Organization and Assembly

Language
Outline

 Overview of Assembly Language


 Assembly Language Syntax
 SimpleRisc ISA
 Functions and Stacks
 SimpleRisc Encoding

2
What is Assembly Language
 A low level programming language uses simple statements that
correspond to typically just one machine instruction. These
languages are specific to the ISA.
 The term “assembly language” refers to a family of low-level
programming languages that are specific to an ISA. They have a
generic structure that consists of a sequence of assembly
statements.
 Typically, each assembly statement has two parts: (1) an
instruction code that is a mnemonic for a basic machine
instruction, and (2) and a list of operands.

3
Assemblers

 Assemblers are programs that convert programs written in


low level languages to machine code (0s and 1s)
 Examples :
 nasm, tasm, and masm for x86 ISAs
 On a linux system try :
 gcc -S <filename.c>
 filename.s is its assembly representation
 Then type: gcc filename.s (will generate a binary: a.out)

4
View of Registers
 Registers → named storage locations
 in ARM : r0, r1, … r15
 in x86 : eax, ebx, ecx, edx, esi, edi

 Machine specific registers (MSR)


 Examples : Control the machine such as the speed of fans, power control
settings
 Read the on-chip temperature.

 Registers with special functions :


 stack pointer
 program counter (points to the address of the currently executing instruction)
 return address

5
View of Memory

 Memory
 One large array of bytes
 Each location has an address
 The address of the first location is 0, and increases by 1 for each
subsequent location
 The program is stored in a part of the memory
 The program counter contains the address of the current
instruction

6
Storage of Data in Memory
 Data Types
 char (1 byte), short int(2 bytes), regular int (4 bytes), long int (8 bytes)

 How are multibyte variables stored in memory ?


 Example : How is a 4 byte integer stored ?
 Save the 4 bytes in consecutive locations
 Little endian representation (used in ARM and x86) → The LSB is stored in
the lowest location
 Big endian representation (Sun Sparc, IBM PPC) → The MSB is stored in the
lowest location

7
Little Endian vs Big Endian

Big endian
87 65 43 21
0 1 2 3
0x87654321
Little endian
21 43 65 87
0 1 2 3

 Note the order of the storage of bytes

8
Storage of Arrays in Memory
 Single dimensional arrays. Consider an array of integers : a[100]

a[0] a[1] a[2]

 Each integer is stored in either a little endian or big endian format


 2 dimensional arrays :
 int a[100][100]
 float b[100][100]
 Two methods : row major and column major

9
Row Major vs Column Major
 Row Major (C, Python)
 Store the first row as an 1D array
 Then store the second row, and so on...
 Column Major (Fortran, Matlab)
 Store the first column as an 1D array
 Then store the second column, and so on
 Multidimensional arrays
 Store the entire array as a sequence of 1D arrays

10
Outline

 Overview of Assembly Language


 Assembly Language Syntax
 SimpleRisc ISA
 Functions and Stacks
 SimpleRisc Encoding

11
Assembly File Structure : GNU
Assembler
Assembly File
.file

.text

.data

 Divided into different sections


 Each section contains some data, or assembly instructions

12
Meaning of Different Sections
 .file
 name of the source file
 .text
 contains the list of instructions
 .data
 data used by the program in terms of read only variables, and
constants

13
Structure of a Statement

Instruction operand 1 operand 2 operand n

 instruction
 textual identifier of a machine instruction
 operand
 constant (also known as an immediate)
 register
 memory location

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Examples of Instructions

sub r3, r1, r2


mul r3, r1, r2

 subtract the contents of r2 from the contents of


r1, and save the result in r3
 multiply the contents of r2 with the contents of
r1, and save the results in r3

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Generic Statement Structure
Label : Directive @ Comment
Constant /* Comment */
Assembly
instruction
 label → identifier of a statement
 directive → tells the assembler to do something like declare
a function
 constant → declares a constant
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Generic Statement Structure - II

Label : Directive @ Comment


Constant /* Comment */
Assembly
instruction
 assembly statement → contains the assembly instruction,
and operands
 comment → textual annotations ignored by the assembler

17
Types of Instructions
 Data Processing Instructions
 add, subtract, multiply, divide, compare, logical or, logical and

 Data Transfer Instructions


 transfer values between registers, and memory locations

 Branch instructions
 branch to a given label

 Special instructions
 interact with peripheral devices, and other programs, set machine specific
parameters

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Nature of Operands

 Classification of instructions
 If an instruction takes n operands, then it is said to be in the n-address
format
 Example : add r1, r2, r3 (3 address format)

 Addressing Mode
 The method of specifying and accessing an operand in an assembly
statement is known as the addressing mode.

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Register Transfer Notation
 This notation allows us to specify the semantics of
instructions
 r1 ← r2
 transfer the contents of register r2 to register r1

 r1 ← r2 + 4
 add 4 to the contents of register r2, and transfer the contents to register r1

 r1 ← [r2] (memory load operation)


 access the memory location that matches the contents of r2, and store the
data in register r1

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Addressing Modes
 Let V be the value of an operand, and let r1, r2 specify registers
 Immediate addressing mode
 V ← imm , e.g. 4, 8, 0x13, -3 ( add r1, r2, 4 ……..here 4 is imm)
 Register direct addressing mode
 V ← r1
 e.g. r1, r2, r3 …

 Register indirect
 V ← [r1]

 Base-offset : V ← [r1 + offset], e.g. 20[r1] (V ← [20+r1])

21
Register Indirect Mode
 V ← [r1]

r1

value
register file

memory

22
Base-offset Addressing Mode

 V ← [r1+offset]

r1
offset

value
register file

memory

23
Addressing Modes - II
 Base-index-offset
 V ← [r1 + r2 + offset]
 example: 100[r1,r2] (V ← [r1 + r2 + 100])

 Memory Direct
 V ← [addr]
 example : [0x12ABCD03]

 PC Relative
 V ← [pc + offset]
 example: 100[pc] (V ← [pc + 100])

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Base-Index-Offset Addressing Mode

 V ← [r1+r2 +offset]

r1
offset
r2
value
register file

memory
25
Outline

 Overview of Assembly Language


 Assembly Language Syntax
 SimpleRisc ISA
 Functions and Stacks
 SimpleRisc Encoding

26
SimpleRisc
 Simple RISC ISA
 Contains only 21 instructions
 We will design an assembly language for SimpleRisc
 Design a simple binary encoding,
 and then implement it ...

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Survey of Instruction Sets
ISA Type Year Vendor Bits Endianness Registers
VAX CISC 1977 DEC 32 little 16
RISC 1986 Sun 32 big 32
SPARC
RISC 1993 Sun 64 bi 32
RISC 1992 Apple,IBM,Motorola 32 bi 32
PowerPC
RISC 2002 Apple,IBM 64 bi 32
RISC 1986 HP 32 big 32
PA-RISC
RISC 1996 HP 64 big 32
CISC 1979 Motorola 16 big 16
m68000
CISC 1979 Motorola 32 big 16
RISC 1981 MIPS 32 bi 32
MIPS
RISC 1999 MIPS 64 bi 32
Alpha RISC 1992 DEC 64 bi 32
CISC 1978 Intel,AMD 16 little 8
x86 CISC 1985 Intel,AMD 32 little 8
CISC 2003 Intel,AMD 64 little 16
RISC 1985 ARM 32 bi(little default) 16
ARM
RISC 2011 ARM 64 bi(little default) 31

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