Chapter 01 Assembly Language
Chapter 01 Assembly Language
Language
Outline
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What is Assembly Language
A low level programming language uses simple statements that
correspond to typically just one machine instruction. These
languages are specific to the ISA.
The term “assembly language” refers to a family of low-level
programming languages that are specific to an ISA. They have a
generic structure that consists of a sequence of assembly
statements.
Typically, each assembly statement has two parts: (1) an
instruction code that is a mnemonic for a basic machine
instruction, and (2) and a list of operands.
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Assemblers
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View of Registers
Registers → named storage locations
in ARM : r0, r1, … r15
in x86 : eax, ebx, ecx, edx, esi, edi
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View of Memory
Memory
One large array of bytes
Each location has an address
The address of the first location is 0, and increases by 1 for each
subsequent location
The program is stored in a part of the memory
The program counter contains the address of the current
instruction
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Storage of Data in Memory
Data Types
char (1 byte), short int(2 bytes), regular int (4 bytes), long int (8 bytes)
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Little Endian vs Big Endian
Big endian
87 65 43 21
0 1 2 3
0x87654321
Little endian
21 43 65 87
0 1 2 3
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Storage of Arrays in Memory
Single dimensional arrays. Consider an array of integers : a[100]
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Row Major vs Column Major
Row Major (C, Python)
Store the first row as an 1D array
Then store the second row, and so on...
Column Major (Fortran, Matlab)
Store the first column as an 1D array
Then store the second column, and so on
Multidimensional arrays
Store the entire array as a sequence of 1D arrays
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Outline
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Assembly File Structure : GNU
Assembler
Assembly File
.file
.text
.data
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Meaning of Different Sections
.file
name of the source file
.text
contains the list of instructions
.data
data used by the program in terms of read only variables, and
constants
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Structure of a Statement
instruction
textual identifier of a machine instruction
operand
constant (also known as an immediate)
register
memory location
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Examples of Instructions
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Generic Statement Structure
Label : Directive @ Comment
Constant /* Comment */
Assembly
instruction
label → identifier of a statement
directive → tells the assembler to do something like declare
a function
constant → declares a constant
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Generic Statement Structure - II
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Types of Instructions
Data Processing Instructions
add, subtract, multiply, divide, compare, logical or, logical and
Branch instructions
branch to a given label
Special instructions
interact with peripheral devices, and other programs, set machine specific
parameters
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Nature of Operands
Classification of instructions
If an instruction takes n operands, then it is said to be in the n-address
format
Example : add r1, r2, r3 (3 address format)
Addressing Mode
The method of specifying and accessing an operand in an assembly
statement is known as the addressing mode.
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Register Transfer Notation
This notation allows us to specify the semantics of
instructions
r1 ← r2
transfer the contents of register r2 to register r1
r1 ← r2 + 4
add 4 to the contents of register r2, and transfer the contents to register r1
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Addressing Modes
Let V be the value of an operand, and let r1, r2 specify registers
Immediate addressing mode
V ← imm , e.g. 4, 8, 0x13, -3 ( add r1, r2, 4 ……..here 4 is imm)
Register direct addressing mode
V ← r1
e.g. r1, r2, r3 …
Register indirect
V ← [r1]
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Register Indirect Mode
V ← [r1]
r1
value
register file
memory
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Base-offset Addressing Mode
V ← [r1+offset]
r1
offset
value
register file
memory
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Addressing Modes - II
Base-index-offset
V ← [r1 + r2 + offset]
example: 100[r1,r2] (V ← [r1 + r2 + 100])
Memory Direct
V ← [addr]
example : [0x12ABCD03]
PC Relative
V ← [pc + offset]
example: 100[pc] (V ← [pc + 100])
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Base-Index-Offset Addressing Mode
V ← [r1+r2 +offset]
r1
offset
r2
value
register file
memory
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Outline
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SimpleRisc
Simple RISC ISA
Contains only 21 instructions
We will design an assembly language for SimpleRisc
Design a simple binary encoding,
and then implement it ...
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Survey of Instruction Sets
ISA Type Year Vendor Bits Endianness Registers
VAX CISC 1977 DEC 32 little 16
RISC 1986 Sun 32 big 32
SPARC
RISC 1993 Sun 64 bi 32
RISC 1992 Apple,IBM,Motorola 32 bi 32
PowerPC
RISC 2002 Apple,IBM 64 bi 32
RISC 1986 HP 32 big 32
PA-RISC
RISC 1996 HP 64 big 32
CISC 1979 Motorola 16 big 16
m68000
CISC 1979 Motorola 32 big 16
RISC 1981 MIPS 32 bi 32
MIPS
RISC 1999 MIPS 64 bi 32
Alpha RISC 1992 DEC 64 bi 32
CISC 1978 Intel,AMD 16 little 8
x86 CISC 1985 Intel,AMD 32 little 8
CISC 2003 Intel,AMD 64 little 16
RISC 1985 ARM 32 bi(little default) 16
ARM
RISC 2011 ARM 64 bi(little default) 31
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