• Today's document is VerilogNetlist and the basics of SDC

and DFT.
• You may already know some of it.
• If you would like me to teach you something a little
more difficult, please let me know what it is.
• I will prepare the documents for you.
• This document is a brief overview, but I think it will be
useful for future work if you keep it in mind.
• Please note that some parts may be slightly different
when explained in detail.
Design Flow
Logical design RTL SDC for system UPF for logical

Logic synthesis Netlist wo DFT

DFT synthesis Netlist w DFT SDC for DFT

ISO/LS Insertion Netlist w DFT/MV UPF for physical

Physical design GDS Package data

Manufacture
PnR Flow (basis)
 Check for syntax errors in provided data such as Netlist/SDC/UPF/Frame data, etc.
Init Design &  Check that the power routing, placementblockage, bounds are correct before executing
FloorPlan PlaceOpt.

 Check cell density and routing congestion.

PlaceOpt  Check Setup Timing. (Is these a floorplan modification or a feedback to SDC?)
 Check Hold Timing. (Check for large value errors. These are due to possible SDC issues.)

 Check the Latency and Skew of each clock

CTS  Check the results of clock routing. (If routing shorts or DRC violations are frequent,
countermeasures are required.)

 Check cell density and routing congestion.

PostCTSOpt  Check Setup Timing. (Is these a floorplan modification or a feedback to SDC or CTS?)
 Check Hold Timing. (Check for large value errors. These may require modification of the CTS
or may need to be countermeasures in the critical path.)

Route  Check the results of routing.

 Check for setup and hold timing to make sure it is not getting very worse.

 Check cell density and routing results. (Can you proceed to TimingECO?)
RouteOpt  Check for setup and hold timing. (Can you proceed to TimingECO?)
 Also run STA to check correlation.
 PnR Flow (basis)
Assume various data provided is correct
PlaceOpt will be the difference between the logical synthesis.
• Therefore, the timing degradation and congestion can be attributed to
floorplan factors or a netlist with poor routability.
PostCTSOpt is the difference from PlaceOpt.
• Therefore, timing degradation and congestion can be attributed to CTS.
RouteOpt is the difference from PostCTSOpt.
• Therefore, timing degradation and congestion can be attributed to
routability.
Comparing(analyzing) the results of each process in
these ways is a shortcut to problem solving.
Similarly, it is important to compare the previous results
when a new PnR is executed.
• Since the optimization of each process is executed several times,
the logs allow us to compare the process even in the middle of the
 input CLK; Verilog Netlis
module test (CLK, RESET, IN_DATA, OUT_DATA)

input REST
input [1:0] IN_DATA;
output OUT_DATA;

wire w_clk_inv, w_clk_div;

Gate Level wire

wire
w_data_0, w_data_1;
w_nand;

Schematic // {cell_name} {instance_name} (.{cell_pin_name(net_name)}, … );

Verilog RTL
module test (CLK, RESET, IN_DATA, OUT_DATA) FFRST
FF_CLK_DIV(.CK(CLK), .RST(RESET), .DATA(w_clk_inv), .Q(w_clk_div)
);
input CLK; INV CLK_INV(.A(w_clk_div), .YB(w_clk_inv) );
input REST
input [1:0] IN_DATA; FF
output OUT_DATA; FF_DATA_IN_0(.CK(w_clk_div), .DATA(IN_DATA[0]), .Q(w_data_0) );
FF
FF_DATA_IN_1(.CK(w_clk_div), .DATA(IN_DATA[1]), .Q(w_data_1) );
always @(negedge RESET or posedge CLK) {
if (!RESET) FF_CLK_DIV = 1’b0; NAND DATA_NAND(.A(w_data_1), .B(w_data_0), .YB(w_nand) );
else FF_CLK_DIV = ~FF_CLK_DIV;
} FF FF_DATA_OUT(.CK(w_clk_div), .DATA(w_nand), .Q(OUT_DATA) );
endmodule
always @(posedge FF_CLK_DIV) {
FF_DATA_IN = IN_DATA;
}

always @(posedge FF_CLK_DIV) {

FF_DATA_OUT = ~(IN_DATA[0] & IN_DATA[1]);
endmodule I haven't written RTL in a few years so I could be wrong.
 STA(Static Timing Analysis)
• Once upon a time, when there was no STA
 Logical verification(Dynamic) was performed and verified.
 It was very difficult and time consuming to verify all paths.

• P(process), V(voltage), T(temperature)

 These are conditions determined on a product-by-product basis.
 Therefore, each scenario will be verified. (ex. worstLT, bestHTTCW, etc)
 Sign-off scenarios(condition) vary by customer and usage process.

• OCV(On-Chip Variation)
 OCV, as the name implies, is the manufacturing variation within a single product.
 These are included in the derating factor and verified in each scenario.

• Statistical Static Timing Analysis

It is almost never the case that all cells in the analysis path are
OCV-worst/best.
Currently, there are various STA methods based on statistics.
 STA(Static Timing Analysis)
• GBA(Graph Based Analysis) and PBA(Path Base Analysis)
The following inverter delays are determined by the input
transition and output capacitance.

What about that transition?

GBA: Apply the worst case on both paths of the A/B pins of the
NAND cell to the YB pin transitions. (pessimistic, but TAT is
better)
PBA: Analyzed by applying the transitions of the path it passes
through.
STA(Static Timing Analysis)
Setup/Hold Timing

OCV Setup Hold

Clock Reconvergence
Common path No need No need
Pessimism Removal
Launch clock Apply max. delay Apply min. delay
path
Data path Apply max. delay Apply min. delay
Capture clock Apply min. delay Apply max. delay
STA(Static Timing Analysis)
Minimum Pulse Width Buffer

OCV High Pulse Low Pulse

Common path No need No need
Rising path Apply max. delay Apply min. delay
Falling path Apply min. delay Apply max. delay
SDC

Other Other
① ②
Block Block

① Defined by set_input_delay and set_input_trantision

② Defined by set_output_delay and set_output_load
SDC(CLK definition)

edge 1 2 3 4 5
time 0 5 10 15 20 25 30

CLK

FF_CLK_DIV/ Q

create_clock –name SYS_CLK –period 10 –waveform {0 5} [get_ports CLK]

create_generate_clock –name SYS_CLK_DIV2 –divide_by 2 –source [get_ports CLK]

[get_pins FF_CLK_DIV/Q]
or
create_generate_clock –name SYS_CLK_DIV2 –edges {1 3 5} –source [get_ports CLK]
[get_pins FF_CLK_DIV/Q]
 SDC(multi cycle definition)
launch clock
hold setup • No multicycle setting
capture clock

launch clock
hold setup • Case with Setup to Multi 2
capture clock set_multicycle_path -end -setup -from launch_clock -to capture_clock 2

launch clock
hold setup
• Case with add Hold Multi 1
capture clock set_multicycle_path -end -setup -from launch_clock -to capture_clock 2
set_multicycle_path -end -hold -from launch_clock -to capture_clock 1

launch clock
hold setup
• Case with Setup to 3 and Hold to 2
capture clock set_multicycle_path -end -setup -from launch_clock -to capture_clock 3
set_multicycle_path -end -hold -from launch_clock -to capture_clock 2
 DFT(Used in manufacturing tests)

• 1st(SCAN_MODE:enable) → scan_shift mode

The red line becomes effective and sets any value to each FF. (from SCAN_IN)
• 2nd(SCAN_MODE:disable) → scan_capture mode
Gray line is enabled and the combinational logic(NAND) is operated.
• 3rd(SCAN_MODE:enable) → scan_shift mode
The red line becomes valid and outputs the value of FF. (to SCAN_OUT)
If the output value is different at this time, it means that there is a malfunction.
 Each Verification
Basically, all customer sign-off requirements must be clean.
• Depending on the situation, they may be mitigated.

Verification Remark
Static Timing Analysis May be mitigated.
Physical Verification must be fixed
May be mitigated by verification conditions
Power Integrity
and timing margins.
Formal Verification must be fixed
Logical Design Rule
must be fixed
Check