Address Decoding

 Address decoder design methodology

 Full address decoder
 Partial address decoder

11-1
 Function of Address
Decoder
Data bus
D15:0
Address bus

A23:1

Parallel Serial
ROM RAM
68000 I/O I/O

Address

decoder
AS
Chip selects

 To transfer data correctly and prevent system damage, only one device at a time
should be allowed to drive the data bus.
 The address decoder selects and enables one and only one data transfer device at
a time.
 The decoder decodes (detects) the value of the address bus based on the memory
map

11-2
 Memory
Map
 When implementing a system the
designer creates a memory map.
 Map would include where RAM, 00 0000
ROM and I/O are. ROM
64K bytes
 Useful Constants: 00 FFFE

 $400 = 1 kilo = 10 lines Unuse

 $1000 = 4 kilo 40 0000
RAM
 $4000 = 16 kilo
64K bytes
 $100000 = 1 Mega 40 FFFE

Unused

FF C000
I/O registers
1024 bytes
FF FFFE

Flight-68k memory map

11-3
 Address Decoding
Strategy
M bits to memory
( A1 - A M ) EPROM
Address bus or
(M+N bits) SRAM

N bits to decoder CS
( AM+1 - A23 )
Address SEL
AS decoder

Address bus Valid

Must activate
SEL only when
AS = 0 because AS
address bus in
invalid at other SEL
times

11-4
 How Many Bits to
Decode?
 In general,
 memories have many internal locations € many lines connect direct to
address bus.
 I/O devices have very few location € few connections to addr bus
 Examples memory chips:
 6164 8KB SRAM or 2764 8KB EPROM:
 13 address lines to chip
 # address lines to decoder € 24 – 13 = 9
 27C040 512KB EPROM
 19 address lines to chip
 #address lines to decoder € 24 – 19 = 5
 Examples I/O chips:
 68230 PI/T
 32 registers € 5 address lines (RS1-RS5) but must connect to A1-A5
 List of address lines to decoder € A23 .. A6 = 17
 74HC574 latch or 74HC541 buffer
 8 bits € 1 address exactly € no addr line to device
 All address lines go to decoder

11-5
 Address Decoding
Methods

Full address decoding Partial address decoding

All the address lines are used to specify a Since not all the address space is
memory location implemented, only a subset of the address
Each physical memory location is identified lines are needed to point to the physical
by a unique address memory locations
Each physical memory location is identified
by several possible addresses (using all
combinations of the address lines that
were not used)

11-6
 Implementing Address
Decoders
 Combinational logic
 AND, NAND, OR, NOR, NOT
 High speed (propagation signals)
 High chip-count
 Lacks flexibility
 Decoders
 2-to-4, 3-to-8, etc
 More appropriate than random logic
 The selection of devices is determined by the physical wiring
 All the memory blocks must have the same size
 Other methods (beyond the scope of the lecture) are
 Programmable Array Logic (PAL)
 Programmable Address Decoders
 Programmable Read Only Memory (PROM)
 Field Programmable Gate Arrays (FPGA) – Most complex & elegant. A single
chip can provide all necessary glue logic (memory control, DTACK generator &
address decoder).

11-7
 Memory Decoder
Design Steps
1. Determine range of address for each device:
 Find starting address (base address)
 Find memory system size (#bytes provided per device group)
 Find ending address
2. Determine which address lines go to decoder
 Find #address lines on device
 Low address go direct from µP to memory
 Remaining address lines to go memory decoder -> find required pattern
to decode
3. Design decoder to detect the required address bus pattern
 Write starting address in binary
 Write ending address in binary
 High order address bits that go to decoder must match in both starting &
ending addresses
 Draw circuit to detect these high order bits

© 2006-2008 [email protected]

11-8
 Example 1
 Design the decoding circuit for interfacing 2764 EPROMs with a basic
68000 system. Assume that the 2764 chips is the only memory
device used.

1. Find address range

 Find starting address
 All ROMs for basic system must start at $000000
 Find memory system size
 Each 2764 chip has 8KB in 8k x 8 organization -> covers only one half of data
bus
 To provide data for upper/lower data bus, must use 2 chips
 2 chips will provide 8 KB x 2 = 16 KB = 16 x 1024 = 16384 bytes
 Write down 16384 in hex -> $4000
 Find ending address
 Ending address = starting address + memory system size – 1
 0 + $4000 – 1 = $3FFF

11-9
 Example 1 cont
2. Determine which address lines to go decoder
 Find # address lines go to memory
system
#lines = log22(16384)
(memory=system
log2(16 size)
x 1024)
= log2 (24 x 210)
= 14 lines A14 – A23 A0 – A13

 Low address go to memory system

0000 0000 00xx xxxx xxxx xxxx
 lowest 14 lines of µP internal address bus ->
A0 to A13
 A0 is internal to µP -> just ignore 0000 0000 0000 0000 0000 0000 ($000000)
 A1 – A13 of µP go to A0 - A12 of every chip
 Remaining address to decoder 0000 0000 0011 1111 1111 1111 ($003FFF)
 A14 – A23

To decoder To memory
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 X X XXX X XXX X XXX X

11-10
 Example 1 cont
3. Design decoder to detect the required address A23
bus pattern
 Starting Address = $000000: A22
= 0000 0000 0000 0000 0000 0000
A20
 Ending address = $003FFF:
A21
= 0000 0000 0011 1111 1111 1111
 Write this range in short form A19 SEL
= 0000 0000 00xx xxxx xxxx xxxx
 Bits that are not x are the bits that must be A18
detected:
 A23-A14 = 0000 0000 00
 AS* = 0 A17
SEL will be low
A16
AS when µP is
To decoder To memory
accessing any
A15
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 12 0 address in the
A14 range $000000 -
0 0 0 0 0 0 0 0 0 0 X XXX X XXX X XXX X
X $003FFF

11-11
 Example 2
 A circuit containing 64K words of RAM is to be
interfaced to a 68000-based system
 The first address of RAM (the base address)
is at
$480000
 What is the entire range of RAM addresses?
 Design a FULL address decoder
 Solution
 The address range for the RAM is from $480000 to
$480000+(128K=$20000)-1=$4A0000-1=$49FFFF

11-12
 Example 3
 Design a full address decoder for a
68000-based system that contains
 2MB of EPROM at a starting
address $00 0000 using 512Kx8
chips
 2MB of RAM at a starting
address
$20 0000 using 256Kx8 chips
 64KB I/O space starting at
$FF0000
 SOLUTION
 For the EPROM we will need 4
* chips,
512Kx8 * organized as 2 pairs
of 512x8 chips (in order to use
UDS /LDS ). We will call these pairs
ROM1 and ROM2
 For the RAM we will need 8 256Kx8
chips, organized as 4 pairs of
256Kx8: RAM1 to RAM4
11-13
 Example 3
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ROM1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X
ROM2 0 0 0 1 X X X X X X X X X X X X X X X X X X X X
RAM1 0 0 1 0 0 X X X X X X X X X X X X X X X X X X X
RAM2 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X
RAM3 0 0 1 1 0 X X X X X X X X X X X X X X X X X X X
RAM4 0 0 1 1 1 X X X X X X X X X X X X X X X X X X X
I/O 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X

A23

A22 ROM2SEL*

A21

A20
AS*

A23

A22
RAM4SEL*

A21

A20

A19
AS*

11-14
 Partial Decoding
The memory space covered by all memory chip is usually much less than the full 16 MB space addressable
by the 68k

For systems with not more than 8 different devices, using the 74HC138 decoder is better solution

Each device occupy block of same size

11-15
 74HC138
Inputs HC family is compatible with
Outputs
Enable Select original HMOS 68000, low-
power HCMOS 68HC000 &
E1 E2 E3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LS logic family.
X X 1 X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1 ‘HC138
0 X X X X X 1 1 1 1 1 1 1 1 A0 Y0
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1 A1 Y1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
A2
1 0 0 0 1 1 1 1 1 0 1 1 1 1
Y2
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
E1 Y3
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
E2 Y4
 When chip is not enabled: all 8 outputs high independent
E3 of A inputs
 Y5
When chip enabled (E1*,E2*,E3=001) only one output goes low, rest high
 Inputs A2,A1,A0 select which of 8 outputs goes low
Y6

Y7
11-16
 Example 4 – Partial Decoder for
Simple System
‘HC138
00 0000 ROM1 A21 A0 Y0 $000000-$1FFFFF (ROM1)
2MB $100000-$3FFFFF (RAM)
20 0000 RAM A22 A1 Y1 $400000-$5FFFFF (ROM2)
A2 Y2 $600000-$7FFFFF
2MB
40 0000 A23 Y3 $800000-$9FFFFF
ROM2
2MB VCC Y4 $A00000-$BFFFFF (PER1)
60 0000 E1 Y5 $C00000-$DFFFFF (PER2)
Unused GND Y6 $E00000-$FFFFFF (PER3)
80 0000 AS E2 Y7
Unused *
A23 E3 A21
A22 A20 A19 A18 A17 A16 --- A1 A0 Block
A0 0000 size =
ROM1 0 0 0 y y y X X --- x X
Peripheral1 memory
RAM 0 0 1 y y y X X --- x X
2MB size /
C0 0000 ROM2 0 1 0 y y y X X --- x X
Peripheral2 PER1 1 0 1 y y y X X --- x X #decoder
2MB PER2 1 1 0 Y Y Y X X --- X X outputs
E0 0000 = 16
PER3 1 1 1 y y y X X --- x X
Peripheral3 Connection To decoder No Connect Direct to Device MB / 8
2MB = 2 MB

11-17
 Mirror Effect in Partial
Decoding
 When device size < block size, aliasing
or mirroring occurs
 Device will respond to >1 address
 Example: using 27C010 (512k x 8)
device in 2 MB block
 ‘010 has 17 lines
 A1-A17 go direct to ‘010 chips
 A21-A23 go to decoder
 A18-A20 unconnected € chip has 7
aliases
 Device will respond anytime A21-A23 =
000
 e.g. CLR $100000 will have same effect
as CLR $000000
 Same effect for rest of decoder outputs
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ROM1 Z Z Z y y y x x x x x x x x x x x x x x x x x x
Connection To decoder No Connect To memory chip

11-18
Example 5 – Alternative Partial
Decoding Scheme
00 0000 ROM1
03 FFFE
256KB
04 0000
RAM
07 FFFE 256KB
08 0000
ROM2
0B FFFE
0C 0000 256KB
0F FFFE Unused
10 0000
13 FFFE Unused
14
0000
17 FFFE Peripheral1
18 256KB  E
a ch block si 25 K6B.
0000
1B FFFE Peripheral2 
1C 0000 256KB
Instead of A18-A20 unconnected, we
1F FFFE Peripheral3
can have A21-A23 unconnected
20 0000 256KB (see analysis for ROM1 below)
 We can use A21 as additional enable to
FF FFFE Unused
reduce aliasing
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ROM1 y y y z z z x x x x x x x x x x x x x x x x x x
Connection No Connect To decoder To memory chip

11-19
 Example 6 – System with
16 Devices ‘HC138 00 000
A18 A0 Y0 ROM1* ROM1 256KB
 Each block is 256KB. 04 0000
 ROM2 256KB
A21 is used to select top A19 A1 Y1 ROM2*
decoder (A21=0) or bottom 08 0000 ROM3 256KB
A2
decoder (A21=1) A20 Y2 ROM3* 0C 0000 ROM4 256KB
VCC RAM2*
10 0000
E1 Y3 ROM4* RAM1 256KB
A21 = 0 completes A21 E2 14 0000
decoder enables for RAM2 256KB
AS* Y4 RAM1*
top decoder 18 0000
E3 ‘HC138
A18 A0 Y0
Y5
Unused
A19 A1 Y1
Y6
A2 38 0000
PI/T 32 bytes
A20 Y2
Y7
3C 0000
A21 DUART 16 bytes
A21 = 1 completes E1 Y3 PIT* 40 0000
decoder enables for
GND E2 DUART* Unused
bottom decoder Y4 FF FFFE
AS
* E3A12
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Y5
ROM1 y y w z z z x x x x x x x x x x x x x x x x x x
Connection N.C. To decoder To memory chip
Y6

Y7

11-20
 Example 3
Revisited

Use 1-to-
2
decoder
Use 2-to-4
Use 3-to- decoder. Can
8 use ‘HC138 or Can be fully
decoder simpler ‘HC139 decoded or
ignored
altogether

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ROM1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X
ROM2 0 0 0 1 X X X X X X X X X X X X X X X X X X X X
RAM1 0 0 1 0 0 X X X X X X X X X X X X X X X X X X X
RAM2 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X
RAM3 0 0 1 1 0 X X X X X X X X X X X X X X X X X X X
RAM4 0 0 1 1 1 X X X X X X X X X X X X X X X X X X X
I/O 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X

11-21
 2-Stage
Decoders
1-to-2 decoder
A20
‘HC138 ($000000-$1FFFFF) ROM1SEL*
A21 A0 Y0
($000000-$1FFFFF)
A22
A1 Y1 ROM2SEL*
A23 A2 2-to-4 decoder
Y2
‘HC138
VCC A17 A0 Y0 RAM1SEL*
E1 Y3 A18
($E00000-$FFFFFF)
GND A1 Y1 RAM2SEL*
AS E2 Y4 GND A2
‘HC138
* A17 A0 Y0 Y2
Y4 RAM3SEL*
E3
Y5 VCC E1
Bypass decoder and A18 A1 Y1 Y3
Y5 RAM4SEL*
take IOSEL* signal here
Y6 A2 GND E2
if aliasing is acceptabl
A19 Y2 E3 Y6
Y7 A20
E1 Y3 Y7

A16 IOSEL*
E2 Y4

E3
Y5

11-22
Y6
 Example 7 – EASy68K
Hardware Model
 ROM is not defined in the simulator!
 ROM exists in all systems but a simulator is not a real system.
 You must have ROM to implement TRAP #15 routines.
 You can write your program anywhere!
 This does not happen in a real system
 Let’s create something close € EZ68k
00 0000 Reserved I/O Locations
4 KB E0 0000 LED Digit 1
00 1000 E0 000 LED Digit 2
E0 0004 LED Digit 3
E0 0006 LED Digit 4
User RAM
E0 0008 LED Digit 5
1 MB
E0 LED Digit 6
000A LED Digit 7
E0 000C LED Digit 8
E0 0000 E0 LED x 8
I/O Space & Stack
RAM 000E
E0 0012 Rocker switch

FF FFFE 2 MB 0010 Pushbutton switch

E0 0014

11-23
 EZ68k Memory
Map

00 0000 E0 0000 LED Digit 1

User RAM
E0 0002 LED Digit 2
2 MB
E0 0004 LED Digit 3
20 0000 E0 0006 LED Digit 4
ROM
E0 0008 LED Digit 5
2
MB E0 LED Digit 6
40 0000 000A LED Digit 7
Unused E0 000C LED Digit 8
E0 LED x 8
E0 0000 I/O Space 000E Rocker switch
1 MB E0 0010 Pushbutton switch
F0 0000 Stack RAM 0012
E0 0016
FF FFFE 1 MB E0 0014
EF FFFE

11-24
 EZ68k Decoder
Worksheet
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

User RAM 0 0 0 x x x x x x x x x x x x x x x x x x x x x
ROM 0 0 1 x x x x x x x x x x x x x x x x x x x x x
7SLED #1 1 1 1 0 0 0 0 0 0
7SLED #2 1 1 1 0 0 0 0 1 0
7SLED #3 1 1 1 0 0 0 1 0 0
7SLED #4 1 1 1 0 0 0 1 1 0
7SLED #5 1 1 1 0 0 1 0 0 0
7SLED #6 1 1 1 0 0 1 0 1 0
7SLED #7 1 1 1 0 0 1 1 0 0
7SLED #8 1 1 1 0 0 1 1 1 0
LED8 1 1 1 0 1 0 0 0 0
Rocker 1 1 1 0 1 0 0 1 0
Pushbutton 1 1 1 0 1 0 1 0 0
Stack RAM 1 1 1 1 x x x x x x x x x x x x x x x x x x x x

Use 3-to-8 Use 4-to-16

Use 1-to-2
decoder decoder
decoder
(1xHC138) (2xHC138)

11-25
Decoder
Circuit

11-26
 Wrong Way to
Connect ROM
 A0 = UDS/LDS
 A1-A14
micro€ both
ROMs A0-A13
 ROM1 = D8-D15
 ROM2 = D0-D7
 Address
decoder selects
ROMs for
A16,A17,A18=000
 ROM: $0000 -
$03FFF, other 138
outputs used for other
devices, RAM etc

© 2006-2008 [email protected] 11-27

 Connecting
RAM
 Addition of two 32K x 8
RAM to previous slide
( two of ROM of last slide
not shown for clarity )
 Again pair for 16bits
wide
 ROM A16-A18=000
 RAM A16-A18=001
 Now R/~W needed
 DTACK* as long as either
ROM or RAM accessed.

© 2006-2008 [email protected] 11-28

 16 bit wide
ROM

 D0-D15 ROM€uP
 All uP A1-A16

• € ROM A0-A15
 64k x 16 ROM

CE* from 138

decoder when
A17,A18,A19=000
•Other
0 0 0 x x x x x x x x x x x x x x x xcombinations for
00000H-0FFFFH
other devices
ROM 0 0 1  As
………………………………………………………………….. ROM
Next all accesses
Device
0 1 0 ………………………………………………………………… are read so
10000H€ *OE=CE*
Another
 DTACK* low
Device20000H€
11-29
• while ROM selected
Connecting LEDs
 Need a byte-wide output port
 The LEDs cannot be connected directly to data bus
 Difficult to select the LEDs
 LEDs would only display value for very short period of time (about
400ns, or 2 clock cycles)
 Only when data bus carries the correct signal
 Microprocessor cannot sink enough current

11-30
Connecting LEDs
 Instead, we need to capture the values on the data bus, and
hold them until changed
 The 74HC374 octal latch will do nicely
 Latch is very fast (around 20 ns), so DTACK* does not need
to be delayed.
 Needs only 1 memory address.

68000 Data bus 74HC374

11-31
Connecting LEDs

68000 Data bus 74HC374

Address
bus 74HC138
decoder

11-32
74LS373 &
74LS374

11-33
 Elementary Output
with 68000

68000 74HC374

D0-D7
or D0-D7
D8-D15

A1-A23 Address
CP
AS
decoder
Vcc

DTACK

DTACK sources
from other devices

11-34
 Connecting
Switches
 Need a byte-wide input port
 Switches cannot be connected directly to data bus
 Must transfer switch values to data bus at the correct time
 A tri-state buffer chip will be just the thing

11-35
74LS244 & 74LS541 Octal 3-State
Buffer/Line Driver

11-36
Elementary Input
with 68000
68000 Buffer

D0-D7
or D0-D7
D8-D15

A1-A23 Address
OE
AS decoder

V cc

DTACK

Other DTACK
sources

11-37
 An Alternative Decoder for
Glue Logic
 74LS139 Decoder
 Contains 2 x 2-to-4 decoders in one chip
 Only one enable per decoder
1A0 1Y0

Inputs 1A1 1Y1

Outputs
Enable Select
1E 1Y2
E A1 A0 Y0 Y1 Y2 Y3 1Y3
1 X X 1 1 1 1
0 0 0 0 1 1 1
2A0 2Y0
0 0 1 1 0 1 1
2A1 2Y1
0 1 0 1 1 0 1
0 1 1 1 1 1 0 2E 2Y2
2Y2

11-38
 Using FPGA or CPLD as
Glue Logic
 The most elegant solution for glue logic!
 FPGA (Field-Programmable Gate Array) or CPLD (Complex
Programmable Logic Device) is a very attractive device
capable of implement ALL glue logic functions in one chip
 Decoder
 Memory read/write enables
 DTACK generator including wait states
 BERR generator
 Must program using Verilog or VHDL language
 Example chips:
 Xilinx 9572 CPLD
(http://www.kmitl.ac.th/%7Ekswichit%20/68k/68ksbc.pdf)

11-39
 Using PLD for Glue
Logic
 Simpler than FPGA or CPLD
 Several versions:
 PAL (programmable array logic) – programmable OR gates, fixed AND
gates, may contain flip-flops, programmable once
 GAL (general array logic) – replaces PAL, reprogrammable
 ROM
 PLA (programmable logic array)
 To implement DTACK & BERR, designer must know internal
architecture of each device to avoid using too many chips
 To program GAL or PLA, may need to know another
language such as ABEL

11-40
 Reference
•© 2006-2008 [email protected]