• Binary Logic and Gates

• Boolean Algebra
• Standard Forms
• Two-Level Optimization
• Map Manipulation ( K-MAP)
• Logic families/ Characteristics
• Negative and Positive Logic
• Transmission Gate

1
Binary Logic and Gates
 Binary logic deals with binary variables
(i.e. can have two values, “0” and “1”)
 Binary variables can undergo three basic
logical operators AND, OR and NOT:

• AND is denoted by a dot (·)

• OR is denoted by a plus (+).
• NOT is denoted by an overbar ( ¯ ), a
single quote mark (') after the variable.

2
 Operator Definitions and Truth
Tables
 Truth table - a tabular listing of the values of a
function for all possible combinations of values
on its arguments
 Example: Truth tables for the basic logic
operations:
AND OR NOT
X Y Z = X·Y X Y Z = X+Y X Z=X
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1
1 1 1
3
Boolean Operator Precedence
 The order of evaluation in a Boolean
expression is:
1. Parentheses
2. NOT
3. AND
4. OR
 Consequence: Parentheses appear
around OR expressions
 Example: F = A(B + C)(C + D)

4
Logic Gates
 In the earliest computers, switches were opened
and closed by magnetic fields produced by
energizing coils in relays. The switches in turn
opened and closed the current paths.
 Later, vacuum tubes that open and close current
paths electronically replaced relays.
 Today, transistors are used as electronic
switches that open and close current paths.

5
Logic Gates
 The building blocks used to create digital circuits
are logic gates
 There are three elementary logic gates and a range
of other simple gates
 Each gate has its own logic symbol which allows
complex functions to be represented by a logic
diagram
 The function of each gate can be represented by a
truth table or using Boolean notation

6
NOT Gate

7
AND Gate

8
OR Gate

9
Other Gate Types
 Why?
• Easier to implement on a chip than the AND, OR
gates
• Convenient conceptual representation

(IBM)
A
B

A
B

(Intel)

10
NAND Gate (Universal Gate)

11
NOR Gate (Universal Gate)

12
NAND Gate as Universal Gate
NAND gate implementation for realizing NOT Gate
x x'

NAND gate implementation for realizing AND Gate

x (x.y)'
x.y
y
NAND gate implementation for realizing OR Gate

x x'
x+y
y y'
13
NOR Gate as Universal Gate
NOR gate implementation for realizing NOT Gate

x x'
NOR gate implementation for realizing AND Gate
x x'
x.y
y
y'
NOR gate implementation for realizing OR Gate

x (x+y)'
x+y
y

14
 Exclusive OR/ Exclusive NOR

 The eXclusive OR (XOR) function is an important

Boolean function used extensively in logic
circuits:
• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
 The eXclusive NOR function (XNOR) is the
complement of the XOR function
 XOR and XNOR gates are complex gates (built
from simpler gates, such as AND, Not, etc).

15
X-OR Gate

16
X-NOR Gate

17
XOR Implementations
 The simple SOP implementation uses the
following structure: X

X ÅY = XY +XY X Y

Y
 A NAND only implementation is:
X

X Y

18
Gate Delay

 In actual physical gates, if one or more input

changes causes the output to change, the output
change does not occur instantaneously.
 The delay between an input change(s) and the
resulting output change is the gate delay denoted
by tG:

1
Input
0
tG tG tG = 0.3 ns
1
Output
0
0 0.5 1 1.5 Time (ns)
19
 Boolean Algebra
 Boolean Constants
• these are ‘0’ (false) and ‘1’ (true)
 Boolean Variables
• variables that can only take the vales ‘0’ or ‘1’
 Boolean Functions
• each of the logic functions (such as AND, OR and NOT) are
represented by symbols as described above
 Boolean Theorems
• a set of identities and laws – see text for details

20
 Boolean Algebra
 Boolean algebra deals with binary variables and
a set of three basic logic operations: AND (.), OR
(+) and NOT ( ) that satisfy basic identities

Basic identities
1. X + 0= X 2. X. 1=X Existence 0 and 1 or
3. X+ 1=1 X . 0=0 operations with 0 and 1
4.
5. X + X= X 6. X .X =X Idempotence
7. X + X=1 8. X .X =0 Existence complements
9. X = X Involution

Replace “+” by “.”, “.” by +,

Dual “0” by “1” and “1’’ by”0”
21
 Boolean Algebra
Boolean Theorems of multiple variables
10. X + Y =Y + X Commutative 11. XY =YX
12. (X + Y) + Z = X + (Y+ Z) Associative 13. (XY)Z =X(YZ )
14. X (Y+ Z) = XY+XZ Distributive 15. X+ YZ = (X + Y)(X + Z)

16. X + Y = X . Y DeMorgan’s 17. X . Y = X + Y

Dual

22
Example: Boolean Algebraic Proof
 A + A·B = A (Absorption
Theorem)
Proof Steps Justification
(identity or theorem)
A + A·B
=A·1+A·B (Operation with 1)
= A · ( 1 + B) (Distributive Law)

=A·1 (Operation with 1)

=A
23
 Exercise
 Simplify Y+X’Z+XY’ using Boolean
algebra Justification
Y+X’Z+XY’ (COMMUTATIVE Property)
= Y+XY’+X’Z (Distributive)
=(Y+X)(Y+Y’) + X’Z (Existence compl.)

=(Y+X).1 + X’Z (0peration with 1)

= Y+X+X’Z (Distributive)
=Y+(X+X’)(X+Z) (Existence compl.)
=Y+1.(X+Z) = X+Y+Z (Operation with 1)

24
 Complementing Functions
 Use DeMorgan's Theorem to
complement a function:
1. Interchange AND and OR
operators
2. Complement each constant value and
literal
X + Y =X .Y X . Y =X + Y

25
 Example: DeMorgan’s theorem

Exercise: find G
F = AB + C (E+D)
G = UX(Y+VZ)

Find F
F = AB + C (E+D)

F = AB . C (E+D)
Answer:
F = (A+B) .(C + (E+D)) G = U’+X’ + Y’V’+Y’Z’
F = (A+B) .(C + E.D)

26
Exercise

Example: Complement G = (a + bc)d + e

G=

27
Other useful Theorems
Dual
 XY + XY = Y Minimization (X + Y)(X + Y) = Y

 X + XY = X Absorption X(X + Y) = X

 X + XY = X + Y Simplification X(X + Y) = XY

 XY + XZ + YZ = XY + XZ Consensus

(X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)

28
Proof the Consensus Theorem
 AB + AC + BC = AB + AC (Consensus Theorem)
Proof Steps Justification (identity or theorem)
AB + AC + BC
= AB + AC + 1 · BC operation 1
= AB +AC + (A + A) · BC existence
= AB + AC + ABC + ABC distributive
= AB + ABC + AC + ABC commutative
= AB(1+C) + AC(1+B) distributive
= AB.1 + AC.1 operation with 1
= AB + AC operation with 1

29
 General Strategies
1. Use idempotency to eliminate terms:
X + X =X X . X=X

2. Complimentarily orX existence

+ X=1 X . X=0
complements:
X + XY = X X(X + Y) = X
3. Absorption: X + XY = X + Y X(X + Y) = XY
4. Adsorption: X + Y =X .Y X . Y =X + Y
5. DeMorgan: XY + XZ + YZ = XY + XZ
6. Consensus: (X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)
30
Standard (Canonical) Forms
 It is useful to specify Boolean
functions in a form that:
• Allows comparison for equality.
• Has a correspondence to the truth
tables
 Canonical Forms in common usage:
• Sum of Products (SOP), also called Sum
of Minterms (SOM)
• Product of Sum (POS), also called
Product of Maxterms (POM)

31
Minterms
 Minterms are AND terms with every variable
present in either true or complemented form.
 Example: Two variables (X and Y)produce
2 x 2 = 4 minterms:
XY
XY
XY
XY
 Given that each binary variable may appear normal
(e.g., x) or complemented (e.g., x ), there are 2n
minterms for n variables.

32
Maxterms
 Maxterms are OR terms with every variable in
true or complemented form.
 There are 2n maxterms for n variables.
 Example: Two variables (X and Y) produce
2 x 2 = 4 combinations:

X +Y
X +Y
X +Y
X +Y

33
Maxterms and Minterms
 Examples: Two variable minterms and
maxterms.
Index Minterm Maxterm
0 (00) xy x+y
1 (01) xy x+y
2 (10) xy x+y
3 (11) xy x+y
 The index above is important for describing
which variables in the terms are true and which
are complemented.

34
Purpose of the Index
 For Minterms:
• “1” in the index means the variable is “Not
Complemented” and
• “0” means the variable is “Complemented”.
 For Maxterms:
• “0” means the variable is “Not Complemented”
and
• “1” means the variable is “Complemented”.

35
 Index Examples – Four Variables
Index Binary Minterm Maxterm
i Pattern mi Mi

form
order in a standard
are in alphabetical
Notice: the variables
0 0000 abcd abcd
1 0001 abcd ?
3 0011 ? a+b+c+d
5 0101 abcd a+b+c+d
7 0111 ? a+b+c+d
10 1010 abcd a+b+c+d
13 1101 abcd ?
15 1111 abcd a+b+c+d
Relationship between min and MAX term?
M i = mi mi = M i 36
 Implementation of a function with
minterms
Function F1(x,y,z) defined by its truth table:
x y z index F1
000 0 0
001 1 1 F1 = x’ y’ z + x y’ z’ + x y z
010 2 0
011 3 0 Thus F1 = m1 + m4 + m7
100 4 1
101 5 0
110 6 0 Short hand notation: F1 = (1,4,7)
m
111 7 1
also called, little m notation

37
Minterm Function Example
 F(A, B, C, D, E) = m2 + m9 + m17 + m23
 F(A, B, C, D, E) write in standard form:
A’B’C’DE’ + A’BC’D’E + AB’C’D’E + AB’CDE
m2 m9 m17 m23

 Sum of Product (SOP) expression:

• F = Σm(2, 9, 17, 23)

38
 Converting a function into a
SOP form: F(A,B,C) = A+B’C
 Write the function as a canonical SOP (with minterms)
 There are three variables, A, B, and C which we take to
be the standard order.
 To add the missing variables:
“ANDing” any term that has a missing variable
with a term 1=( X + X’).
 F=A+B’C = A(B+B’)(C+C’) + B’C(A+A’)
= ABC + ABC’ + AB’C + AB’C’ + AB’C + A’B’C
= ABC + ABC’ + AB’C + AB’C’ + A’B’C
= m7 + m6 + m5 + m4 + m1
= m1 + m4 + m5 + m6 + m7

39
Expressing a function with
Maxterms
 Start with the SOP: F1(x,y,z) =m1 + m4 + m7
 Thus its complement F1can be written as
• F1 = m0 +m2 +m3 + m5 + m6 (missing term of F1)
 Apply deMorgan’s theorem on F1:
• (F1 = (m0 +m2 +m3 + m5 + m6)
= m0.m2.m3.m5.m6
= M0.M2.M3.M5.M6
= ΠM(0,2,3,5,6) also called, Big M notation
Thus the Product of Sum terms (POS):
F1 = (x + y + z) ·(x + y + z)·(x+ y + z)
·(x + y + z)·(x + y + z)
40
Canonical Product of Maxterms
 Any Boolean Function can be expressed as a
Product of Sums (POS) or of Maxterms (POM).
• For an expression, apply the second
distributive law , then “ORing” terms
missing variable x with a term equal to
0=(x.x’) and then applying the distributive
law again.
F(A,B,C)= A+A’B’
Apply the distributive law:
F= A+A’B’ = (A+A’)(A+B’)
= 1.(A+B’)
Add missing variable C: F= A+B’+CC’
= (A+B’+C)(A+B’+C’)
= M2.M3 41
Alternatively: use Truth Table
 For the function table, the maxterms used
are the terms corresponding to the 0's.
F(A,B,C)= A+A’B’
ABC F
000 1
001 1
010 0 M2 F = M2.M3
011 0 M3
= (A+B’+C)(A+B’+C’)
100 1
101 1
110 1
111 1
42
Function Complements
 The complement of a function expressed as a
sum of minterms is constructed by selecting the
minterms missing in the sum-of-product
canonical forms.
 Alternatively, the complement of a function
expressed by a Sum of Products form is simply
the Product of Sums with the same indices.
 Example: Given
F ( x , y , z ) = Sm ( 1, 3 , 5 , 7 )
F( x, y , z ) = Sm(0, 2,4,6)
F( x, y , z ) = PM(1, 3,5,7 )

43
A Simplification Example
 Simplify F F( A , B, C) m(1,4,5,6,7 )
 Writing the minterm expression:
F = A’ B’ C + A B’ C’ + A B C’ + AB’C + ABC
 Simplifying using Boolean algebra:
F=

44
Circuit Optimization
 Goal: To obtain the simplest
implementation for a given function
 Optimization is a more formal approach
to simplification that is performed using
a specific procedure or algorithm
 Optimization requires a cost criterion to
measure the simplicity of a circuit
 Distinct cost criteria we will use:
• Literal cost (L)
• Gate input cost (G)
• Gate input cost with NOTs (GN)
Chapter 2 - Part 2 45
Literal Cost
 Literal – a variable or it complement
 Literal cost – the number of literal appearances
in a Boolean expression corresponding to
the logic circuit diagram
 Examples:
• F = AB+C(D+E) L=5
• F = AB+CD+CE L=6
• Which solution is best?

G  ABCD  A B C D L 8
G ( A  B)( B  C )(C  D)( D  A) L 8

Which is best? The same complexity?

Chapter 2 - Part 2 46
Literal Cost
 Examples:
• F = BD+AB’C+AC’D’ L=
• F = BD+AB’C+AB’D’+ABC’ L=
• F = (A+B)(A+D)(B+C+D’)(B’+C’+D) L=
• Which solution is best?

Chapter 2 - Part 2 47
 Gate Input Cost
 Gate input costs - the number of inputs to the gates in the
implementation corresponding exactly to the given equation or
equations. (G - inverters not counted, GN - inverters counted)
 For SOP and POS equations, it can be found from the equation(s)
by finding the sum of:
• all literal appearances
• the number of terms excluding single literal terms,(G) and
• optionally, the number of distinct complemented single literals (GN).
 Example:

G  ABCD  A B C D G 8  2 10, GN 8  2  4 14

G ( A  B )( B  C )(C  D)( D  A) G ? GN ?
• Which solution is best?

Chapter 2 - Part 2 48
 Cost Criteria (continued)
 Example : GN = G + 2 = 9
 F=A+ BC+ BC L= 5
G=L+2= 7
B
C
A F

 L (literal count) counts the AND inputs and the single

literal OR input.
 G (gate input count) adds the remaining OR gate inputs
 GN(gate input count with NOTs) adds the inverter inputs

Chapter 2 - Part 2 49
 Cost Criteria (continued)
 Example : A
 F = A B C + AB C B
C
 L = 6 G = 8 GN = 11 F
 F = (A + )( + C)( + B)
C B A
 L = 6 G = 9 GN = 12
 Same function and same
literal cost A
 But first circuit has better B
gate input count and better C
gate input count with NOTs F
 Select it!
=> Gate input cost performs better.

Chapter 2 - Part 2 50
Cost Criteria
 F1=AB+C(D+E)
 F2=AB+CD+CE

 F3=ABCD+A’B’C’D’
 F4=(A’+B)(B’+C)(C’+D)(D’+A)

Chapter 2 - Part 2
 Boolean Function Optimization
 Minimizing the gate input (or literal) cost of a (a set of)
Boolean equation(s) reduces circuit cost.
 We choose gate input cost.
 Boolean Algebra and graphical techniques are tools to
minimize cost criteria values.
 Some important questions:
• When do we stop trying to reduce the cost?
• Do we know when we have a minimum cost?
=> Optimization problem
 Treat optimum or near-optimum cost functions
for two-level (SOP and POS) circuits first.
 Introduce a graphical technique using Karnaugh maps (K-
maps, for short)
Chapter 2 - Part 2 52
Karnaugh Maps (K-map)
 A K-map is a collection of squares
• Each square represents a minterm
• The collection of squares is a graphical representation
of a Boolean function
• Adjacent squares differ in the value of one variable
• Alternative algebraic expressions for the same function
are derived by recognizing patterns of squares
 The K-map can be viewed as
• A reorganized version of the truth table

Chapter 2 - Part 2 53
Some Uses of K-Maps
 Provide a means for:
• Finding optimum or near optimum
 SOP and POS standard forms, and
 two-level AND/OR and OR/AND circuit
implementations
for functions with small numbers of
variables
• Visualizing concepts related to manipulating
Boolean expressions, and
• Demonstrating concepts used by computer-
aided design programs to simplify large
circuits
Chapter 2 - Part 2 54
 Two Variable Maps
 A 2-variable Karnaugh Map:
• Note that all the adjacent minterms are
differ in value of only one variable

Chapter 2 - Part 2 55
From Truth Tables to K-Map
 K-Maps can be used to simplify Boolean functions by
systematic methods. Terms are selected to cover the
1’s cells in the map.
 Example – Two variable function:

Result of simplification :
F A  B
Chapter 2 - Part 2 56
K-Map Function Representation

Example : G ( A, B)  A B  AB

Result of simplification=?

Chapter 2 - Part 2 57
 Three Variable Maps
 A three-variable K-map:

 Where each minterm corresponds to the product

terms:
yz=00 yz=01 yz=11 yz=10
x=0 x y z xyz xyz xyz
x=1 x y z xyz xyz xyz
 Note that if the binary value for an index differs in one
bit position, the minterms are adjacent on the K-Map

Chapter 2 - Part 2 58
Three-Variable Maps
 Reduced literal product terms for SOP standard
forms correspond to rectangles on K-maps
containing cell counts that are powers of 2.
 Rectangles of 2 cells represent 2 adjacent
minterms; of 4 cells represent 4 minterms that
form a “pairwise adjacent” ring.
• 2 cells rectangle will cancel 1 variable
• 4 (=22 ) cells rectangle will cancel 2 variables
• 8 (=23 ) cells rectangle will cancel 3 variables
 What is the result for this case in three variables K-map?

Chapter 2 - Part 2 59
 Three Variable Maps
 Example : Simplify
F (A, B ,C ) m(0, 1, 2, 3, 4, 5)

Result:

F ( A, B ,C )  A  B
Chapter 2 - Part 2 60
 Three Variable Maps
 Example : Simplify
G ( A, B, C ) m(0, 2, 4, 5, 6)

Result:

G ( A, B ,C )  AB  C
Chapter 2 - Part 2 61
 Three Variable Maps
 Example : Simplify
H ( A, B ,C ) m(1, 3, 4, 5, 6)

Result:
H ( A, B ,C )  A C  AB  AC
Chapter 2 - Part 2 62
Three-Variable Map Simplification
 Use a K-map to find an optimum SOP
equation for F(X, Y, Z) m(0,1,2,4,6,7)

Chapter 2 - Part 2 63
Four Variable Maps
 Map and location of minterms:

Chapter 2 - Part 2 64
Four Variable Terms

 Four variable maps can have rectangles

corresponding to:
• A single 1 = 4 variables, (i.e. Minterm)
• Two 1s = 3 variables,
• Four 1s = 2 variables
• Eight 1s = 1 variable,
• Sixteen 1s = zero variables (i.e.
Constant "1")

Chapter 2 - Part 2 65
Four-Variable Maps
 Example : Simplify
F (A, B ,C , D) m(0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13)

Result:
F C  A D  B D
Chapter 2 - Part 2 66
Four-Variable Maps
 Example : Simplify
G ( A, B ,C , D)  A C D  A D  B C  CD  AB D

Result:
G B D  A C  CD
Chapter 2 - Part 2 67
Four-Variable Map
 F(W, X, Y, Z) = Sm(3,4,5,7,9,13,14,15)

Chapter 2 - Part 2 68
 Map Manipulation
1. Implicant: X is an implicant of Boolean function F if and only if
wherever X takes 1 F will be 1.
2. A Prime Implicant : an implicant is said to be prime implicant if it is not
part of any other implicant. It is a product term obtained by combining
the maximum possible number of adjacent squares in the map into a
rectangle with the number of squares a power of 2.
3. Essential Prime Implicant :A prime implicant is called an Essential
Prime Implicant if it is the only prime implicant that covers (includes)
one or more minterms.
4. Redundant Prime Implicants : the prime implicant for which each of its
term is covered by some essential prime implicant.
5. Selective Prime Implicants
The prime implicants for which are neither essential nor redundant
prime implicants are called selective prime implicants(SPI). These are
also known as non-essential prime implicants. They may appear in some
solution or may not appear in some solution.
Chapter 2 - Part 2 69
Example
Example
F(W, X, Y, Z) = Sm(1,5,6,7,11,12,13,15)
Example
Given F = ∑(0, 1, 5, 8, 12, 13), find number of implicant,
PI, EPI, RPI and SPI
 Example
Given F = ∑(0, 1, 5, 7, 15, 14, 10), find number of
implicant, PI, EPI, RPI and SPI.
 Example of Prime Implicants
 Find ALL Prime Implicants
CD ESSENTIAL Prime Implicants
C C
BD BD
1 1 1 1 1 1

BD 1 1 BD 1 1
B B
1 1 1 1
A A
1 1 1 1 1 1 1 1
AB
D D
AD Minterms covered by single prime implicant
BC
Chapter 2 - Part 2 74
Another Example
 Find all prime implicants for:
G(A, B, C, D) m(0,2,3,4,7,12,13,14,15)
• Hint: There are seven prime implicants!

Chapter 2 - Part 2 75
Product-of-Sums Optimization
 The minterm not included in the function belong
to the complement of the function.
 Example : F(A, B, C, D) m(0, 1, 2, 5, 8, 9, 10)

F AB  CD  BD
F (A  B)( C  D)(B  D)
Don't Cares in K-Maps
 Sometimes a function table or map contains entries for
which it is known:
• the input values for the minterm will never occur, or
• The output value for the minterm is not used
 In these cases, the output value need not be defined
 Instead, the output value is defined as a “don't care”
 By placing “don't cares” ( an “x” entry) in the function table
or map, the cost of the logic circuit may be lowered.
 Example 1: A logic function having the binary codes for the
BCD digits as its inputs. Only the codes for 0 through 9 are
used. The six codes, 1010 through 1111 never occur, so the
output values for these codes are “x” to represent “don’t
cares.”

Chapter 2 - Part 2 77
 Don’t care example
WXYZ Digit a b
 BCD code on a 0000 0 1 1
a=Σm(0,2,3,5,6,7,8,9)+ Σ
seven segment 0001 1 0 1 d(10,11,12,13,14,15)
display: 0010 2 1 1 Y
0011 3 1
0100 4 0 1 1 1
0101 5 1
0110
0111
6
7
1
1
1 1 1
X
1000 8 1
1001 9 1 X X X X
outputs
1010 - X W
a b c d… g 1011 X 1 1 X X
? 1100 X
1101 X Z
WXYZ 1110 X
Input (BCD) 1111 X a=?
78
 Find SOP for segment “a”
a=Σm(0,2,3,5,6,7,8,9)+ Σ d(10,11,12,13,14,15)

a=? Y

1 1 1
1 1 1
X
X X X X
W
1 1 X X

79
Don't Cares in K-Maps
 Example : Simplify
F ( A, B, C , D)  m (1, 3, 7, 11, 15)
d ( A, B, C , D)  m (0, 2, 5)

Chapter 2 - Part 2 80
 Product of Sums Example
 Find the optimum POS solution:
F(A, B, C, D) m(3,9,11,12 ,13,14,15)  d (1,4,6)
C Find prime implicants for F’
0 x 1 0 A’B, B’D’, A’C;

x 0 0 x F’=A’B + B’D’
B
1 1 1 1
Use DeMorgan’s to find F as POS
A
0 1 1 0
Thus F=(A+B’) (B+D)
D

81
 Exercises with don’t cares

 F(A,B,C,D)=Σm(2,5,8,10,13,14) +Σd(0,1,6)

 Write F as minimized SOP:

• F=

 Write F as minimized POS

• F=

82
Multiple-Level Circuit Optimization

 Multiple-level circuits - circuits that are

not two-level (with or without input
and/or output inverters)
 Multiple-level circuits can have reduced
gate input cost compared to two-level
(SOP and POS) circuits
 Multiple-level optimization is performed
by applying transformations to circuits
represented by equations while
evaluating cost
Chapter 2 - Part 2 83
 From two-level circuit to multiple-level circuit

G  ABC  ABD  E  ACF  ADF

Two-level circuit

Gate-input cost =17

Chapter 2 - Part 2 84
 From two-level circuit to multiple-level circuit

G  AB(C  D)  E  A(C  D) F

Multiple-level
circuit

Gate-input cost =13

Chapter 2 - Part 2 85
From two-level circuit to multiple-level circuit

Share (C+D) in the preceding circuit:

Gate-input cost =11

But, G ( AB  AF )(C  D)  E

Chapter 2 - Part 2 86
Product of Sums Example
 Find the optimum POS solution:
F(A, B, C, D) m(3,9,11,12 ,13,14,15) 
d (1,4,6)
• Hint: Use F’ and complement it to get
the result.

87
Exercise: Design a 2-bit comparator
 Design a circuit that has two 2–bit numbers N1
and N2 as inputs, and generates three outputs to
indicate if N1<N2, N1=N2 and N1>N2.

(N1=N2) N1=AB
A F1
B N1 N2=CD
F2 (N1<N2)
N2 F3
C (N1>N2)
D

 Design the circuit as minimized SOP

88
Design a 2-bit comparator - Solution

89
Design a 2-bit comparator - Solution

90
 Odd and Even Functions
 The odd and even functions on a K-map form
“checkerboard” patterns.
 The 1s of an odd function correspond to minterms having
an index with an odd number of 1s.
 The 1s of an even function correspond to minterms
having an index with an even number of 1s.
 Implementation of odd and even functions for greater than
four variables as a two-level circuit is difficult, so we use
“trees” made up of :
• 2-input XOR or XNORs
• 3- or 4-input odd or even functions

91
Example: Odd Function Implementation
 Design a 3-input odd function F = X + Y + Z
with 2-input XOR gates
 Factoring, F = (X+ Y) + Z
 The circuit:

X
Y
F
Z

92
Example: 4-Input Function Implementation
 Design a 4-input odd function F = W + X + Y + Z
with 2-input XOR and XNOR gates
 Factoring, F = (W + X) + (Y + Z)
 The circuit:

W
X
F
Y
Z

93
 Parity Generators and Checkers
 In Chapter 1, a parity bit added to n-bit code to
produce an n + 1 bit code:
• Add odd parity bit to generate code words with even
parity
• Add even parity bit to generate code words with odd
parity
• Use odd parity circuit to check code words with even
parity
• Use even parity circuit to check code words with odd
parity

94
 Parity Generators and Checkers

 Example: n = 3. Generate even parity code words of length four

with odd parity generator:
0
X 0
Y 0
0 X 1
E
Z Error
0 Y 1
P =1 P
1 Z
 Check even parity code words of length four with odd parity
checker

 Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) and E = 0.

95
 Levels of Integration
Integrated Circuit: is a silicon semiconductor crystal containing the
electronic components for the digital gates.

Small-scale integration (SSI):

no of gates less than 10
Simple logic functions, basic storage elements etc.
Medium-scale integration (MSI):
10–100 gates
4-bit adders, 8-to-1 multiplexers,counters, etc.
Large-scale integration (LSI):
100 to a few 1000 gates
Programmable logic array (PLA), PROM, small processors, etc.
Very large-scale integration (VLSI):
several thousand to millions of gates
Processors, large memory array, etc.
Ultra large-scale integration (ULSI):
no of gates > 10 million
Advanced processors, system chips, etc.

96
Digital Logic Families

RTL (Resistor-Transistor Logic):

DTL(Diode-Transistor Logic):
TTL(Transistor-Transistor Logic):
ECL (Emitter-Coupled Logic):
MOS (Metal-Oxide Semiconductor):
CMOS (Complementary Metal-Oxide Semiconductor):

97
Performance Characteristics

Fan-in: Number of inputs available on a gate.

Fan-Out: Number of standard loads that the output of
a typical gate can drive without impairing its
performance.
Noise Margin: The maximum external noise voltage
superimposed on a normal input value will not cause
an undesirable change in the circuit output.
Power Dissipation: Power consumed by the gate and
made available from the power supply.
Power Delay: Delay time for the change in value of a
signal to propagate from input to output.

98
Comparison of Logic Families

99
Propagation Delay for an
Inverter

100
Transient Characteristics
Rise time
The time taken by signal to switch from 10% to 90% of its
normal value
Fall time
The time taken by signal to switch from 90% to 10% of its
normal value
High-low and low-high transition
times at the output of a gate are defined as tHL and tLH
Propagation delay: The signal through a gate take certain
amount of time to propagate from inputs to the output.The
average transition delay for a signal to propagate from input
to output when the binary signals change in value
tPHL, tPLH and tPD

101
Transient Characteristics
tPHL:- the time required for the output signal
to reach 50% of its normal value on the H-to-L
transition after the input signal reached 50%
of its normal signal

tPLH:- the time required for the output signal

to reach 50% of its normal value on the L-to-H
transition after the input signal reached 50%
of its normal signal

tPD:- It is the mean of the above two and is

generally used for hand calculations. And in
early days max of the two quantities
was considered
102
Positive and Negative Logic
High level H represent logic 1 and low level L represent
logic 0 defines a positive- logic system
High level H represent logic 0 and low level L represent
logic 1 defines a negative- logic system
Truth table with H and L Truth table for positive logic
X Y Z X Y Z
L L L 0 0 0
L H L 0 1 0 AND Gate
H L L 1 0 0
H H H 1 1 1
Truth table for Negative logic
X Y Z
1 1 1
1 0 1 OR Gate
0 1 1
0 0 0
103
Transmission Gates
Transmission Gate (TG) is an electronic switch
for connecting and disconnecting two points in a
circuit.
It has four external connections or ports, C and C’
are the control inputs and X and Y are the signals
to be connected or disconnected by the TG.
If C=1 and C’=0, X and Y are connected.
If C=0 and C’=1, X and Y are disconnected.

104
Transmission Gate Conti….
Transmission Gate can be used to construct X-OR gate
connected from two transmission gates and two inverters.

x C TG1 TG0 F
0 0 NP P 0
0 1 P NP 1
1 0 NP P 1
1 1 P NP 0
Note:
NP: No Path
P: Path

105