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VECTORED AND NON

VECTORED INTERRUPTS
DONE BY
DARSHANA R (22L210)
SHAKTHI LAKSHMI S
(22L263)
WHAT IS AN INTERRUPT: 2
• An interrupt is a signal generated by either hardware devices or
software components to interrupt the normal execution of a
program and request immediate attention from the operating
system.
• If the request is accepted, the processor will suspend its current
activities, save its state, and execute a function called an
interrupt handler (or an interrupt service routine, ISR) to deal
with the event.
• This interruption is often temporary, allowing the software to
resume normal activities after the interrupt handler finishes.
• Interrupts are the primary means by which IO devices obtain the
services of the CPU.
• They significantly improve a computer's IO performance by
giving IO devices direct and rapid access to the CPU and by
freeing the CPU from the need to check the status of its IO
INTERRUPT REQUEST- interrupting 3
the CPU is by activating a control line

The CPU identifies the source of

the interrupt, for example, by
polling IO devices.

The CPU obtains the memory address of the

required interrupt handler. This address can
be provided by the interrupting device along
with its interrupt request.
The program counter PC and other CPU
status information are saved as in a
subroutine call.

The PC is loaded with the address of the interrupt

handler. Execution proceeds until a return
instruction is encountered, which transfers control
back to the interrupted program.
SINGLE LINE
INTERRUPT 4

• The interrupt selection method requiring the least hardware is the single-line
method
• All IO ports share a single INTERRUPT REQUEST line.
• CPU scans all the devices to find the source of the interrupt.
• The connection sequence of this line determines the interrupt priority of each
device.
• Alternatively, the CPU can execute a program that polls each device.
• Polling has the advantage of allowing the interrupt priority to be programmed.
MULTIPLE LINE
INTERRUPT 5

• Multiple line or multilevel interrupts, which amounts to independent

requesting of interrupt service.
• Each interrupt request line is assigned a unique priority. The source of the
interrupt is immediately known to the CPU, thus eliminating the need for a
hard ware or software scan of the IO ports.
• Unless further measures are taken, the CPU may still have to execute a
program that fetches the address of the interrupt-service program to be
used.
• This step can be eliminated by another technique called vectoring of
interrupts
VECTORED INTERRUPT:
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• A Vectored Interrupt, a type of interrupt handling mechanism, is a processing
technique in which the interrupting device directs the processor to the
appropriate Interrupt Service Routine.
• In the context of vectored interrupts, when an interrupt occurs, the interrupting
device or component provides the processor with additional information called
a Vector.
• The interrupting device will supply the CPU with the starting address or
Interrupt Vector of the specific interrupt service routine (ISR) associated with
the interrupting device.
• The processor uses the Interrupt Vector to locate the appropriate ISR in a
predefined table or memory location. The ISR is a piece of code that handles
the specific interrupt.
• The ISR performs the necessary actions to handle the interrupt, which may
include saving the current state of the processor, performing specific tasks
related to the interrupt, and restoring the processor's state afterward.
 7
• Each interrupt request line generates
a unique fixed address, which is used
to modify the CPU's program counter
PC.
• The input from the NAND Gates is
given to a Priority Encoder.
• Here, if INT REQ 3 is enabled, all
other interrupts will not be
considered, thus solving the problem
of priority.
• The interrupt mask register can
disable any or all of the interrupt
request lines.
• By setting bit i of this register to 1,
interrupt request line i is disabled
(enabled).
• The k masked interrupt signals are
fed into a priority encoder that
produces a [log2 k]-bit address, which
is then inserted into PC.
• To see how program control is transferred using this type of vectored interrupt,
consider that three devices are connected to four IO ports.
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• Output of priority encoder is given to PC. For example, if device 2 generates
an interrupt signal, priority encoder output would be 2.
• Program Counter can be set by placing 2 in bits 3:2 of PC and the remaining
30 bits of PC (bits 31:4 and 1:0) can be set to 0. Now, PC points to 8 (..000100)
• If IO port 0 generates the interrupt, Priority counter output becomes 0. Thus,
PC points 0. 9
• PC bit (31-4) = 0 : 00 : 00.
• If IO port 1 generates the interrupt, Priority counter output becomes 1. Thus,
PC points 4
• PC bit (31-4) = 0 : 01 : 00.
• If IO port 2 generates the interrupt, Priority counter output becomes 2. Thus,
PC points 8
• PC bit (31-4) = 0 : 10 : 00.
• If IO port 3 generates the interrupt, Priority counter output becomes 3. Thus,
PC points 12
• PC bit (31-4) = 0 : 11 : 00.
• This results in assigning the first four word storage locations of M to interrupt
vectors.
• The contents of these locations are the user-assigned start addresses of the
interrupt-handling
• Routines. The routines themselves are of arbitrary length and can be located
any
where in M.
• The foregoing scheme has a one-to-one correspondence between interrupt
request lines and interrupt handlers.
• If an IO device requires the services of k distinct programs, it needs k distinct interrupt
request lines. 10

• The above vectored interrupt scheme that does not have this restriction.
• Multiple interrupt request lines are used, but each IO port now has its own
interrupt
acknowledge line.
• Each IO port can request the services of many different programs.
• Each IO port now has its own interrupt acknowledge line. 11
• When the CPU activates an acknowledge line, the IO port in question places
the address of the desired interrupt handler on the main data bus.
• This approach requires the interrupting IO port to be able to generate at least
partial memory addresses and to act as a bus master.
• Another possibility is for an IO device to send the CPU an interrupt vector in
the form of a CPU instruction.
• The CPU removes this instruction from the data bus and executes it in the
normal manner.
• Thus if the IO device sends the instruction CALL PROG to the CPU, execution
of this instruction saves essential CPU information, such as the program
counter, and transfers control to an interrupt-handling routine named PROG.
• 8085-based microcomputers use this technique to implement vectored
interrupts
• To reduce the number of external connections to the CPU—an important
consideration in the case of microcontrollers the interrupt-priority control
logic can be external to the CPU
NON VECTORED INTERRUPT:
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• In this type of interrupt, the interrupt address is not known to the processor so, the
interrupt address needs to be sent externally by the device to perform interrupts. For
example: INTR – 8085.
• The device will have to supply the address of the subroutine to the Microprocessor.
The INTR input is the only non-vectored interrupt.
• INTR - It is a maskable interrupt, having the lowest priority among all interrupts. It can
be disabled by resetting the microprocessor.
• When INTR signal goes high, the following events can occur −

 The microprocessor checks the status of INTR signal during the execution of each
instruction.

 When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.

 When instructions are received, then the microprocessor saves the address of the
next instruction on stack and executes the received instruction.
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