What is an Interface ?

In computing, an interface is a shared boundary across which two or more separate components of a
computer system to exchange information.

The exchange can be between software, computer hardware, peripheral devices, humans, and
combinations of these.

Some computer hardware devices, such as a touchscreen, can both send and receive data through
the interface, while others such as a mouse or microphone may only provide an interface to send data
to a given system.

Types of interfaces : Hardware & Software interfaces

Hardware interfaces exist in many of the components, such as the various buses, storage devices,
other I/O devices, etc.

A hardware interface is described by the mechanical, electrical and logical signals at the interface
and the protocol for sequencing them (sometimes called signaling).

A standard interface, such as Small Computer System Interface (SCSI), decouples the design
and introduction of computing hardware, such as I/O devices, from the design and introduction of
other components of a computing system, thereby allowing users and manufacturers great
flexibility in the implementation of computing systems.

A software interface may refer to a wide range of different types of interface at different "levels": an
operating system may interface with pieces of hardware.

Applications or programs running on the operating system may need to interact via data streams,
filters, and pipelines; and

in object oriented programs, objects within an application may need to interact via methods.
In computer system, there are special hardware components between the CPU and peripherals to
control or manage the input-output transfers.

These components are called input-output interface units because they provide communication
links between processor bus and peripherals.

There are two types of interfacing in 8085 - Memory Interfacing & I/O Interfacing.

Programming to the interface

The use of interfaces allows for a programming style called programming to the interface.

The idea behind this approach is to base programming logic on the interfaces of the objects used,
rather than on internal implementation details.

Programming to the interface reduces dependency on implementation specifics and makes more
reusable.

Pushing this idea to the extreme, inversion of control leaves the context to inject the code with the
specific implementations of the interface that will be used to perform the work.
Programmable interface device

A programmable interface device is designed to perform various input/output functions.

Such a device is set up to perform functions by writing an instruction in its internal register, the control
register.

Functions can be changed during program execution by writing a new instruction.

These devices are flexible, versatile and economical and widely used in microprocessor based products.

There are programmable devices for

• Parallel I/O

• Serial I/O

• Interrupt controller

• DMA controller and so on.

Why memory interfacing in microprocessor?

When we are executing any instruction, we need the microprocessor to access the memory for
reading instruction codes and the data stored in the memory.
The interfacing circuit therefore should be designed in such a way that it matches the memory
signal requirements with the signals of the microprocessor.

What is the importance of I O interface?

The purpose of IOP is to provide an independent pathway for the transfer of information
between external device and internal memory.

Asynchronous Data Transfer : This Scheme is used when speed of I/O devices do not match
with microprocessor, and timing characteristics of I/O devices is not predictable.
 Programmable peripheral interface
The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required.

It can be used with almost any microprocessor.

It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per
the requirement.

Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.

Port B is similar to PORT A.

Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4
8255Pin diagram

•PA0 – PA7 – Pins of port A

•PB0 – PB7 – Pins of port B
•PC0 – PC7 – Pins of port C
•D0 – D7 – Data pins for the transfer of
data
•RESET – Reset input
•RD’ – Read input
•WR’ – Write input
•CS’ – Chip select
•A1 and A0 – Address pins
Data Bus Buffer
It is a tri-state 8-bit buffer, which is used to
interface the microprocessor to the system
data bus. Data is transmitted or received by
the buffer as per the instructions by the CPU.
Control words and status information is also
transferred using this bus.
Read/Write Control Logic
This block is responsible for controlling the
internal/external transfer of data/control/status
word. It accepts the input from the CPU
address and control buses, and in turn issues
command to both the control groups.
Expanded version of the control logic
and I/O ports

Chip select logic and port addresses

CS

It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU.

It is connected to the decoded address, and A0 & A1 are connected to the microprocessor
address lines.

Their result depends on the following conditions −

CS A1 A0 Result
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
Control
0 1 1
Register
No
1 X X
Selection
WR

It stands for write.

This control signal enables the write operation.

When this signal goes low, the microprocessor writes into a selected I/O port or control register.

RESET

This is an active high signal.

It clears the control register and sets all ports in the input mode.

RD

It stands for Read.

This control signal enables the Read operation.

When the signal is low, the microprocessor reads the data from the selected I/O port of the 8255.
A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table
showing their various signals with their result.
To communicate with peripherals through 8255, three steps are necessary :

1. Determine the address of ports A, B, C and control register according to

the chip select logic and address lines A0 and A1

2. Writ a control word in the control register

3. Write I/O instructions to communicate with peripherals through ports

A,B and C
Control word format
D0, D1, D3, D4 are assigned for port C lower, port B, port C upper and port A respectively. When

these bits are 1, the corresponding port acts as an input port.

For e.g., if D0 = D4 = 1, then lower port C and port A act as input ports.

If these bits are 0, then the corresponding port acts as an output port.

For e.g., if D1 = D3 = 0, then port B and upper port C act as output ports.

D2 is used for mode selection of Group B (port B and lower port C).

When D2 = 0, mode 0 is selected and when D2 = 1, mode 1 is selected.

D5 & D6 are used for mode selection of Group A ( port A and upper port C).

D7 = 1, as it is I/O mode
Operating modes of 8255
1. Bit set reset (BSR) mode

 The Bit Set/Reset (BSR) mode is available on port C only.

 Each line of port C (PC7 - PC0) can be set or reset by writing a suitable value in the

control word register.

 BSR mode and I/O mode are independent and selection of BSR mode does not affect

the operation of other ports in I/O mode

 In this mode only port C bits can be set or reset.

 By setting the MSB of control word (D7) to 0, PPI works in BSR mode.
Write a BSR control word subroutine to set bits pc7 and pc3 and reset them after 10ms
To set PC7 control word will be D7 D6 D5 D4 D3 D2 D1 D0
As an example, to set PC5, then in the CW is ,
0 0 0 0 1 1 1 1 = 0F H
To reset PC7 control word will be D7 D6 D5 D4 D3 D2 D1 D0
1.Since it is BSR mode, D7 = '0'.
0 0 0 0 1 1 1 0 = 0E H
To set PC3 control word will be D7 D6 D5 D4 D3 D2 D1 D0 2.Since D4, D5, D6 are not used, assume them to be '0'.
0 0 0 0 0 1 1 1 = 07 H
To reset PC3 control word will be D7 D6 D5 D4 D3 D2 D1 D0 3.PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
0 0 0 0 0 1 1 0 = 06 H
MVI A, 0FH // Load byte in accumulator to set PC7 4.PC5 has to be set, hence, D0 = '1'.
OUT 83H // Set PC7=1
Thus, as per the above values, 0B (Hex) will be loaded
MVI A, 07H // Load byte in accumulator to set PC3
OUT 83H // Set PC3=1 into the Control Word Register (CWR).
CALL DELAY // delay routine for 10ms
MVI A, 06H // Load byte in accumulator to reset PC3
OUT 83H // Set PC7=1
MVI A, 0EH // Load byte in accumulator to reset PC7
OUT 83H // Set PC7=1
RET
2. Input-Output mode (I/O mode)
By setting the MSB of control word (D7) to 1, PPI works in input-output mode.
This is further divided into three modes: Mode 0, Mode 1 and Mode 2
Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports.
Each port can be programmed in either input mode or output mode where outputs are
latched and inputs are not latched. Ports do not have interrupt capability.
Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as
either input or output ports. Each port uses three lines from port C as handshake signals.
Inputs and outputs are latched.
Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either
in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data
transfer. The remaining three signals from Port C can be used either as simple I/O or as
handshake for port B.
For example, if port B and upper port C have to be
initialized as input ports and lower port C and port A as
output ports (all in mode 0):

1.Since it is an I/O mode, D7 = 1.

2.Mode selection bits, D2, D5, D6 are all 0 for mode 0

operation.

3.Port B and upper port C should operate as Input

ports, hence, D1 = D3 = 1.

4.Port A and lower port C should operate as Output

ports, hence, D4 = D0 = 0.

Hence, for the desired operation, the control word D7 D6 D5 D4 D3 D2 D1 D0

register will have to be loaded with "10001010" = 8A 1 0 0 0 1 0 1 0

Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals.

Port A, port B provide simple I/O operation.

2 halves of port C can be either used as an additional 8-bit port, or as 2 individual 4-bit ports.

Since the two halves of port C are independent, they may be used such that one-half is initialized as

an input port while the other half is initialized as an output port.

The input/output features in mode 0 are as follows:

1.Output ports are latched.

2.Input ports are buffered, not latched.

3.Ports do not have handshake or interrupt capability.

4.With 4 ports, 16 different combinations of I/O are possible.

'Latched' means the bits are put into a storage register (array of flip-flops) which holds

its output constant even if the inputs change after being latched.

The 8255's outputs are latched to hold the last data written to them.

This is required because the data only stays on the bus for one cycle.

Without latching, the outputs would become invalid as soon as the write cycle finishes.

The inputs are not latched because the CPU only has to read their current values, then

store the data in a CPU register or memory if it needs to be referenced at a later time.

If an input changes while the port is being read then the result may be indeterminate.
Mode 0 – input mode

•In this mode, the 8255 gets data from the external peripheral ports and the CPU reads the received data via its

data bus.

•The CPU first selects the 8255 chip by making CS low. Then it selects the desired port using A 0 and A1 lines.

•The CPU then issues an RD signal to read the data from the external peripheral device via the system data bus

Mode 0 - output mode

•In this mode, the CPU sends data to 8255 via system data bus and then the external peripheral ports receive

this data via 8255 port.

•CPU first selects the 8255 chip by making CS low. It then selects the desired port using A 0 and A1 lines.

•CPU then issues a WR signal to write data to the selected port via the system data bus. This data is then

received by the external peripheral device connected to the selected port.

Write a program to read the DIP switches and display the reading from the PORT B at Port A and
from port C (lower) at port C(upper)

Port addresses: This is a memory

mapped I/O , when the address line
A15 is high the CS is enabled.

Assuming all don’t care lines are at

logic 0, the port addresses are as
follows:
Port A : 8000H ( A1 = 0, A0=0)
Port B : 8001H ( A1 = 0, A0=0)
Port C : 8002H ( A1 = 1, A0=0)
CR : 8003H ( A1 = 1, A0=1)
Control word
MVI A, 83H // Load accumulator with CW

STA 8003H // Write CW into CR

LDA 8001H // Read switches at Port B

STA 8000H /display the read value at Port A

LDA 8002H // Read switches at Port C

ANI 0FH // Mask the upper 4 bits of Port C

RLC // rotate to place Cu in ACC

RLC

RLC

RLC

STA 8002H //display at port Cu

HLT
Design an interfacing ckt to read data from an A/D converter using 8255A in memory – mapped I/O

1. Setup port A to read data

2. Set up bit PC0 to start conversion and bit PC7 to

read the status of the converter.

Configure Port A as input, CL as output, CU as input

and port B not used.

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 1 0 0 0 = 98 H

BSR CW for SoC & EoC ( set and reset PC0 )

D7 D6 D5 D4 D3 D2 D1 D0
Set =01 H
Reset = 00H
0 0 0 0 0 0 0 1/0
SUBROUTINE
LXI H, 8003H // CR
MVI A, 98H // Cw
MOV M,A // CW-> CR
MVI A, 01H // BSR to set PC0
MOV M,A // load ACC with CW
CALL DELAY // delay
MVI A, 00H // reset PC0
Read : MOV M,A
DCX H // Port C
MOV A,M // read port C
RAL // place PC7 in carry
JC READ // wait in loop for EoC
LDA 8000H // Read A/D converter
RET
Mode 1 - Strobed Input/output mode
To use port A or port B for handshake (strobed) input or output operation, initialise that port in mode 1.
Port A and Port B can be initialised to operate in different modes, i.e., for e.g., Port A can operate in
mode 0 and Port B in mode 1.
Some of the pins of port C function as handshake lines.
For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1
and PC2 pins function as handshake lines.
If port A is initialised as mode 1 input port : then, PC3, PC4 and PC5 function as handshake signals.
Pins PC6 and PC7 are available for use as input/output lines.
The mode 1 which supports handshaking has following features:
1.Two ports i.e. port A and B can be used as 8-bit i/o ports.
2.Each port uses three lines of port c as handshake signal and remaining two signals can be used as
i/o ports.
3.Interrupt logic is supported.
4.Input and Output data are latched.
Input configuration Control word and status word format
Mode 1: Input Control Signals

1.STB (Strobed Input) - This signal is active low & generated by the peripheral

device to indicate that it has transmitted a byte of data.

The 8255 in response to STB generates the IBF & INTR.

The strobe input loads data into the port latch, which holds the information until it

is input to the microprocessor via the IN instruction.

2. IBF (Input Buffer Full) - This signal is an acknowledgement by the 8255 to

indicate that the input latch has received the data byte. This is rest when the MPU

reads the data.

3. INTR (Interrupt request) - It is an output that may be used to interrupt the MPU.

This signal is generated if STB, IBF and INTE are all at logic 1.

This is reset by the falling edge of the RD signal.

The INTR pin becomes a logic 1 when the STB input returns to a logic 1, and is

cleared when the data are input from the port by the microprocessor.

4. INTE (Interrupt enable) - It is neither an input nor an output;

it is an internal bit programmed via the port PC4(port A) or PC2(port B) bit

position using the BSR mode.

Timing waveforms for strobed input ( with handshake )
 Programming 8255 in Mode 1

8255 can be programmed to function using either status I/O or interrupt I/O.

Interrupt I/O
Status check I/O
The MPU continuously checks the
status of the IBF line until it goes high
Mode 1 : Output Control signals

Control word and status word format

Output configuration
Mode 1 : Output Control signals

1. OBF (output signal) - This output signal goes low when the MPU writes data into the output latch off

8255. This indicates the peripheral that the new data is ready to read. It goes high after 8255 receives

the ACK from the peripheral.

2. ACK (Input Signal) - The peripheral outputs a low when it receives the data from the 8255 ports.

3. INTR (Interrupt request) - It is an output signal and set by the rising edge of the ACK signal. This is

used to interrupt the MPU to request the next data byte for output.

This signal is set when OBF, ACK and INTE are all high and rest by the falling edge of WR.

4. INTE (Interrupt enable) - It is an internal FF to a port and needs to be set to generate the INTR signal.

The two FF’s INTE A & INTE B) are controlled by the bits PC6 and PC2 through BSR mode.

5. PC4-5 – These two lines can be set as either input or output.

Timing waveforms for strobed output ( with handshake )
Illustration for Mode 1.

Port A is the input port for the keyboard with interrupt I/O

Port B as output for a printer with status check I/O.

1. Find port addresses by analysing the decode logic

2. Determine the control word to setup Port A as input and Port B as output in

Mode 1.

3. Determine the BSR word to enable INTE A (Port A)

4. Determine the masking byte to verify the OBF B line in the status check I/O

(port B)

5. Write initialization instructions and a printer subroutine to output characters

that are stored in memory.

1. Port addresses
Port A : FCH
Port B : FDH
5.Initialization program
Port C : FEH
MVI A, B4 H
Control register : FFH OUT FFH
MVI A,09H
OUT FFH
2. Control word for Mode 1 CALL PRINT

1 0 1 1 1 0 1 0 0 = B4 H Print subroutine

Print : LXI H,MEM

MVI B,COUNT
Next : MOV A,M
3. BSR word MOV C,A
STATUS: IN FEH
0 0 0 0 1 0 0 1 = 09 H ANI 02H
JZ STATUS
MOV A,C
OUT FDH
4. Status word to check OBFB INX H
DCR B
X X X X X X 1 X = 02H ( masking byte) JNZ NEXT
RET
•Here STB signal is used to inform the output device that data is available on the data bus by
the processor.
•Here port A and port B can be separately configured as either input or output port.
•Both the port utilizes 3-3 lines of port C for handshaking signals. The rest two lines operates
as input/output port.
•It supports interrupt logic.
•The data at the input or output ports are latched.
Mode 2 - Strobed Bidirectional Input/Output mode

Only port A can be initialized in this mode.

Port A can be used for bidirectional handshake data transfer.

This means that data can be input or output on the same eight lines (PA0 - PA7).

Pins PC3 - PC7 are used as handshake lines for port A.

The remaining pins of port C (PC0 - PC2) can be used as input/output lines if group B is initialized

in mode 0 or as handshaking for port B if group B is initialized in mode 1.

In this mode, the 8255 may be used to extend the system bus to a slave microprocessor or to

transfer data bytes to and from a floppy disk controller.

Acknowledgement and handshaking signals are provided to maintain proper data flow and

synchronisation between the data transmitter and receiver.