Digital VLSI

Design

Lecture 6:

Moving to the Physical

Domain
 So, what’s Definition and
Planning
next? Design and
Verification
• We’ve basically finished the Front-End of the design
Logic Synthesis
process and we will now start the Back-End:
• To start, we will move between tools with a logical Physical Design
approach to ones with a physical approach to design
implementation. Signoff and Tapeout
• Then, we will make a physical foundation for our
Silicon Validation
• This will
design byinclude
drawing up a
making floorplan.
decisions where “big” or
“important” pieces will sit, such as IPs, I/Os, Power grids,
• After
special routes,
that, etc. place our gates taking into account congestion
we can
and timing.
• With our flip-flops in place, we can go about designing a clock-tree.
• And finally, we can route all our nets, according to DRCs, timing,
noise, etc.
3
• Before tapeout, we will clean things up, verify, etc.
 An illustrative view of Physical
Definition and
Planning
Design and
Verification

Design Logic Synthesis

Physical Design
Signoff and
move Tapeout
Silicon
to
Validation
P&R
tool
Design
Import
Floorpla
Initial floorplan
n
and pad ring
emen
and Pad ri Placement
t

CTS

Route

Finish

Prepare Detailed Route Clock Tree

4 Design
 An illustrative view of Physical
Definition and
Planning
Design and
Verification

Design Logic Synthesis

Physical Design
Signoff and
move Tapeout
Silicon
to
Validation
P&R
tool
Design
Import
an Floorpla
Initial emen n
floorpl Plac t
and Pad Placement
ri
CTS

Route

Finish

4
Prepare Design
 Moving from Logical to
Physical Design
Import
• Define design (.v) Floorpla
• Define design constraints/targets (.sdc) n
Placeme
• Define operating conditions/modes nt
(MMMC) CTS
• Define technology and libraries (.lef) Rout
• Define physical properties e
(Floorplan) Finish
Design

Verilog Physical
netlist Design
Flow GDSII

5
SDC
 Design
Import
Floorpla
n

Moving from Logical to Physical Placemen

t
CTS
• During synthesis, our world view was a bit OFF
Rout

idealistic. 0.9V e
Finish
• We didn’t care about power supplies. 0.7V 0.9V Design

• We didn’t care about physical

MV with power
connections/entities. gating (shut
• We didn’t
Define care nets”
“global about and
clock non-idealities.
how down)
they connect to physical
• Therefore, in order to start physical
instances.
• Provide technology rules and cell abstracts (.lef files)
implementation:
• Provide physical cells, unnecessary for logical functionality:
• Tie cells, P/G Pads, DeCaps, Filler cells, etc.
• Define hold constraints and all operating modes and
conditions (MMMC)
• Hold was “easy to meet” with an ideal clock, so we didn’t really check
it…
6 • Set up “low power” definitions, such as voltage
 1 4 5
2 3
Moving to Hierarchical Power
MSV Floorplanning
Physical Design Design Planning

A bit about
Multiple Voltage
Domains
Often referred to as “Low Power Design” Methodologies

7
 Design
Import
Floorpla
n

Multiple Domain Design Placemen

t
CTS
• Define power domains Rout
e
• Create power domain Finish
Design
names RAM
• List of cells connected to IP
VDD1, VDD2, GND1,… PD1
• Draw the power core
domains PD3 PD2

• Place macros
• Routing congestion ROM
• •Take into account:
Orientation
• Manual usually better then
Auto
• Place switches
• For the power down
8
 Design
Import
Floorpla
n

Multiple Domain Design – Level Shifters Placemen

t
CTS
VDD1 logic Rout
IN VDD model e
Finish
2 Design
OUT
VSS

Double row Shifter

0.7V – Floorplan VDD1
Dual High-to-Low and
1.08V
LS

LS

Low-to-Hight level
shifter
LS

LS

VSS
LS
IN OUT
0.9 0.7
V V VDD1
LS
VDD2

VSS

https://www.vlsicommunity.com
9
Multiple Domain Design – Power
Design
Import
Floorpla
n

Gating VDD
Placemen
t
CTS

Rout
e
Finish
Design
VDD VVDD1 VVDD2 VDD
domain domain

sleep_control
(on/off)
VDD
Glo VDD
VVDD1 VVDD2
VSS

D
VD
D
VD

VVDD1 VVDD2
VDDV

VDD VDD

VVDD1 VVDD2

10
 Design
Import
Floorpla
n

How do we define this? Placemen

t
CTS
• There is a command format for this. Rout
e
• Well, actually two. Finish
Design
• Cadence calls theirs CPF (Common Power Format),
and it’s surprisingly (…confusingly) similar to MMMC.
• Synopsys calls theirs UPF (Unified Power
Format), and it’s surprisingly similar to SDC.

• Luckily for you, we will not talk any more about

this right now .
• Instead, we’ll start with the basics of
Floorplanning.
11
 1 4 5
2 3
Moving to Hierarchical Power
MSV Floorplanning
Physical Design Design Planning

Floorplannin
g
 Floorplanning Goals and Objectives
Design
• Floorplanning is a mapping Import
between the logical description Floorpla
(the netlist) n
and the physical description (the Placeme
floorplan). nt
CTS
• Goals of floorplanning:
• Arrange the blocks on a chip. Rout
• Decide the location of the I/O e
pads. Finish
• Decide the location and Design
number of the power pads.
• Decide the type of power
distribution.
• Decide the location and type 13
 Fullchip Design Overview
• Chip size
Core
• Number of Gates placeme
nt area
• Number of Metal
The location
layers of the core,
• Interface to the I/O areas P/G
pads and the RAM
outside P/G grid IP
Ring
• Hard IPs/Macros P/G
s ROM
Gri
• Power Delivery d
Strap
s
• Multiple Voltages
Peripher
• Clocking Scheme y
• Flat or Hierarchical? (I/O)
14
area
Floorplanning Inputs and
Design
Import
Floorpla
n

Outputs Placemen
t

• Inputs
CTS
• Outputs Rout
• Design netlist (required) • Die/block e
Finish
• Area requirements area Design

(required) • I/Os placed

• Power requirements • Macros
Power grid
• (required)
Physical partitioning placed
designed
• information (required)
Timing constraints • Power pre-routing
• Die
(required)
size vs. performance vs. •
schedule trade-off Standard cell
(required) placement
• Design ready for
• I/O placement (optional) areas cell
standard
• Macro placement placement
information (optional)
15
 Design
Import
Floorpla
n

IO Ring Placemen
t
CTS
• The pinout is often decided by front-end designers, with input Rout

from physical design and packaging engineers. e

Finish
Design
• I/Os do not tend to scale with IO
Moore’s Law and therefore, they are
very expensive
(in terms of area).
• I/Os are not only needed for core
connecting signals to the outside
world, but also to provide power to
the chip.
• Therefore, I/O planning is a critical
and
• Let’s leave very
it at thatcentral stage
for a bit, and in I/Os a little
revisit the
Floorplanning the chip.
later… 16
How do we choose our chip
Design
Import
Floorpla
n

size? Placemen
t
CTS

Route

Finish

Design

“Core “Pad
Limited” Limited” 17
 Design
Import
Flo rpla
o n

Utilization Plact
emen

TS
• Utilization refers to the percentage of core area C
out
that is taken up by standard cells. Re
Desig
• A typical starting utilization might be 70% Finis n
h
• This can vary a lot depending on the design
• High utilization can make it difficult to close a Low standard-
cell
design utilization
• Routing congestion,
• Negative impact during optimization
legalization stages.
• Local congestion
• Can occur with pin-dense cells like
multiplexers, so utilization is not completely
sufficient for determining die size. High standard-
1
• Run a quick trial route to check for routing cell
 Uniquifying the Netlist
• When moving to the physical domain, the netlist must be unique
• A unique netlist, means that each sub-module is only referenced
once.
• In the example, the non-unique netlist cannot optimize instance
m1/u1 module amod1
module amodwithout changing instance m2/u1
bmo bmo
(); BUFFD1 ();
d d BUFFD1 u1 ();
u1 ();
endmodule m m m m endmodule
module bmod module amod2
();
1 2 u11 2 (); BUFFD1 u1
u1 ();
amod u1
u1 endmodule
m1 ; amod module bmod
m2 ; Non-unique (); amod1
endmodule Unique m1 ; amod2 m2
• A synthesized netlist must be uniquified before ; endmodule
placement can begin. This can be done either by
the synthesizer or during design import.
19
 Design
Import
Floorpla
n

Hard Macro Placement Placemen

t

• When placing large macros we must consider impacts on CTS

Rout
routing, timing and power. Usually push them to the sides of e
Finish
the floorplan. Design

• Placement algorithms generally perform better with a

single large rectangular placement area.
• For wire-bond place power hungry macros away from
the chip center.
Possible
• After placing hard macros, mark them as FIXED. routing
congestio
n
hotspots

20
Placement
Design
Import
Floorpla
n

Regions Placemen
t
CTS
• Sometimes, we want to “help” the tool put Rout

certain e
Finish
Design
logic in certain regions or cluster them together.
• Place and Route tools define several types
of placement regions:
• Soft guide – try to cluster these cells
together
without a defined area.
• Guide – try to place the cells in the
• defined area. place the cells in the defined
Fence – must
• Region
area and keep place
– must out allthe
other cells.
cells in the defined
area, but other cells may also be placed
there. 21
 Design
Import

Placement Blockages and Halos

Floorpla
n
Placemen
t
CTS
• Placement blockage halos are areas Rout
that the tools should not place any e
Keepout Finish

• cells.
These, too, have several types: margin
Design

• Hard Blockage – no cells can be

placed inside.
• Soft Blockage – cannot be used
during placement, but may be
used during optimization. RAM5
• Partial Blockage – an area with
lower utilization.
• Halo (padding) – an area
outside a macro that should
be kept clear of standard cells. Pins are on
left and
right 22
 Design

Placement Blockages and Halos

Import
Floorpla
n
Placemen
t
CTS

Route

Finish

Design
Hard blockage
always created
on all four sides

Soft blockage
created only for the
channels between
the macros or
between the macro
and the core
boundary
23
 Design
Import
Floorpla
n

Routing Blockage Placemen

t
CTS
• Similar to placement blockage, Rout

routing blockage can be e

Finish
Design
defined. (75,95)
• Blockage is
defined for a
given layer.
Routin
g
blockag
e

(20,20)

24
Guidelines for a good
Design
Import
Floorpla
n

floorplan
Single
Use blockage
Placemen
t
CTS
RAMS out of toimprove
large pin
core area the way in the Rout

corner accessibili e
Finis Desig
Large ty
RAM RAM RAM h n

routing 1 2 3

channel
RAM s RAM RAM RAM
Avoid 4 5 6
Standard cells constricti
area
ve
RAM channels
RAM Avoid many
•
pins in the RAM
q narrow RAM 8
channel. 7
PLL MY_SUB_BLOCK Rotate for pin
accessibility

Pins away
from
25
corners