Digital VLSI

Design

Lecture 6:

Moving to the Physical

Domain
 So, what’s Definition and
Planning
next? Design and
Verification
• We’ve basically finished the Front-End of the design
Logic Synthesis
process and we will now start the Back-End:
• To start, we will move between tools with a logical Physical Design
approach to ones with a physical approach to design
implementation. Signoff and Tapeout
• Then, we will make a physical foundation for our
Silicon Validation
• This will
design byinclude
drawing up a
making floorplan.
decisions where “big” or
“important” pieces will sit, such as IPs, I/Os, Power grids,
• After
special routes,
that, etc. place our gates taking into account congestion
we can
and timing.
• With our flip-flops in place, we can go about designing a clock-tree.
• And finally, we can route all our nets, according to DRCs, timing,
noise, etc.
3
• Before tapeout, we will clean things up, verify, etc.
 An illustrative view of Physical
Definition and
Planning
Design and
Verification

Design Logic Synthesis

Physical Design
Signoff and
move Tapeout
Silicon
to
Validation
P&R
tool
Design
Import
an Floorpla
Initial emen n
floorpl Plac t
and Pad Placement
ri
CTS

Route

Finish

4
Prepare Design
 Moving from Logical to
Physical Design
Import
• Define design (.v) Floorpla
• Define design constraints/targets (.sdc) n
Placeme
• Define operating conditions/modes nt
(MMMC) CTS
• Define technology and libraries (.lef) Rout
• Define physical properties e
(Floorplan) Finish
Design

Verilog Physical
netlist Design
Flow GDSII

5
SDC
 Design
Import
Floorpla
n

Moving from Logical to Physical Placemen

t
CTS
• During synthesis, our world view was a bit OFF
Rout

idealistic. 0.9V e
Finish
• We didn’t care about power supplies. 0.7V 0.9V Design

• We didn’t care about physical

MV with power
connections/entities. gating (shut
• We didn’t
Define care nets”
“global about and
clock non-idealities.
how down)
they connect to physical
• Therefore, in order to start physical
instances.
• Provide technology rules and cell abstracts (.lef files)
implementation:
• Provide physical cells, unnecessary for logical functionality:
• Tie cells, P/G Pads, DeCaps, Filler cells, etc.
• Define hold constraints and all operating modes and
conditions (MMMC)
• Hold was “easy to meet” with an ideal clock, so we didn’t really check
it…
6 • Set up “low power” definitions, such as voltage
 1 4 5
2 3
Moving to Hierarchical Power
MSV Floorplanning
Physical Design Design Planning

A bit about
Multiple Voltage
Domains
Often referred to as “Low Power Design” Methodologies

7
 Design
Import
Floorpla
n

Multiple Domain Design Placemen

t
CTS
• Define power domains Rout
e
• Create power domain Finish
Design
names RAM
• List of cells connected to IP
VDD1, VDD2, GND1,… PD1
• Draw the power core
domains PD3 PD2

• Place macros
• Routing congestion ROM
• •Take into account:
Orientation
• Manual usually better then
Auto
• Place switches
• For the power down
8
 Design
Import
Floorpla
n

Multiple Domain Design – Level Shifters Placemen

t
CTS
VDD1 logic Rout
IN VDD model e
Finish
2 Design
OUT
VSS

Double row Shifter

0.7V – Floorplan VDD1
Dual High-to-Low and
1.08V
LS

LS

Low-to-Hight level
shifter
LS

LS

VSS
LS
IN OUT
0.9 0.7
V V VDD1
LS
VDD2

VSS

https://www.vlsicommunity.com
9
Multiple Domain Design – Power
Design
Import
Floorpla
n

Gating VDD
Placemen
t
CTS

Rout
e
Finish
Design
VDD VVDD1 VVDD2 VDD
domain domain

sleep_control
(on/off)
VDD
Glo VDD
VVDD1 VVDD2
VSS

D
VD
D
VD

VVDD1 VVDD2
VDDV

VDD VDD

VVDD1 VVDD2

9
 Design
Import
Floorpla
n

How do we define this? Placemen

t
CTS
• Well, we probably will leave that to an advanced course Rout

or your MSc research… e

Finish
Design
• But, in general, there is a command format for this.
• Well, actually two.
• Cadence calls theirs CPF (Common Power Format),
and it’s surprisingly (…confusingly) similar to MMMC.
• Synopsys calls theirs UPF (Unified Power
Format), and it’s surprisingly similar to SDC.
• I guess neither is very common or unified…
• Luckily for you, we will not talk any more about
this right now .
• Instead, we’ll start with the basics of
10
Floorplanning.
 1 4 5
2 3
Moving to Hierarchical Power
MSV Floorplanning
Physical Design Design Planning

Floorplannin
g
 Floorplanning Goals and Objectives
Design
• Floorplanning is a mapping Import
between the logical description Floorpla
(the netlist) n
and the physical description (the Placeme
floorplan). nt
CTS
• Goals of floorplanning:
• Arrange the blocks on a chip. Rout
• Decide the location of the I/O e
pads. Finish
• Decide the location and Design
number of the power pads.
• Decide the type of power
distribution.
• Decide the location and type 12
 Fullchip Design Overview
• Chip size
Core
• Number of Gates placeme
nt area
• Number of Metal
The location
layers of the core,
• Interface to the I/O areas P/G
pads and the RAM
outside P/G grid IP
Ring
• Hard IPs/Macros P/G
s ROM
Gri
• Power Delivery d
Strap
s
• Multiple Voltages
Peripher
• Clocking Scheme y
• Flat or Hierarchical? (I/O)
13
area
Floorplanning Inputs and
Design
Import
Floorpla
n

Outputs Placemen
t

• Inputs
CTS
• Outputs Rout
• Design netlist (required) • Die/block e
Finish
• Area requirements area Design

(required) • I/Os placed

• Power requirements • Macros
Power grid
• (required)
Physical partitioning placed
designed
• information (required)
Timing constraints • Power pre-routing
• Die
(required)
size vs. performance vs. •
schedule trade-off Standard cell
(required) placement
• Design ready for
• I/O placement (optional) areas cell
standard
• Macro placement placement
information (optional)
14
 Design
Import
Floorpla
n

IO Ring Placemen
t
CTS
• The pinout is often decided by front-end designers, with input Rout

from physical design and packaging engineers. e

Finish
Design
• I/Os do not tend to scale with IO
Moore’s Law and therefore, they are
very expensive
(in terms of area).
• I/Os are not only needed for core
connecting signals to the outside
world, but also to provide power to
the chip.
• Therefore, I/O planning is a critical
and
• Let’s leave very
it at thatcentral stage
for a bit, and in I/Os a little
revisit the
Floorplanning the chip.
later… 15
How do we choose our chip
Design
Import
Floorpla
n

size? Placemen
t
CTS

Route

Finish

Design

“Core “Pad
Limited” Limited” 16
 Design
Import
Flo rpla
o n

Utilization Plact
emen

TS
• Utilization refers to the percentage of core area C
out
that is taken up by standard cells. Re
Desig
• A typical starting utilization might be 70% Finis n
h
• This can vary a lot depending on the design
• High utilization can make it difficult to close a Low standard-
cell
design utilization
• Routing congestion,
• Negative impact during optimization
legalization stages.
• Local congestion
• Can occur with pin-dense cells like
multiplexers, so utilization is not completely
sufficient for determining die size. High standard-
• Run a quick trial route to check for routing cell
1  Adam Teman, 201
 Uniquifying the Netlist
• When moving to the physical domain, the netlist must be unique
• A unique netlist, means that each sub-module is only referenced
once.
• In the example, the non-unique netlist cannot optimize instance
m1/u1 module amod1
module amodwithout changing instance m2/u1
bmo bmo
(); BUFFD1 ();
d d BUFFD1 u1 ();
u1 ();
endmodule m m m m endmodule
module bmod module amod2
();
1 2 u11 2 (); BUFFD1 u1
u1 ();
amod u1
u1 endmodule
m1 ; amod module bmod
m2 ; Non-unique (); amod1
endmodule Unique m1 ; amod2 m2
• A synthesized netlist must be uniquified before ; endmodule
placement can begin. This can be done either by
the synthesizer or during design import.
18
 Design
Import
Floorpla
n

Hard Macro Placement Placemen

t

• When placing large macros we must consider impacts on CTS

Rout
routing, timing and power. Usually push them to the sides of e
Finish
the floorplan. Design

• Placement algorithms generally perform better with a

single large rectangular placement area.
• For wire-bond place power hungry macros away from
the chip center.
Possible
• After placing hard macros, mark them as FIXED. routing
congestio
n
hotspots

19
Placement
Design
Import
Floorpla
n

Regions Placemen
t
CTS
• Sometimes, we want to “help” the tool put Rout

certain e
Finish
Design
logic in certain regions or cluster them together.
• Place and Route tools define several types
of placement regions:
• Soft guide – try to cluster these cells
together
without a defined area.
• Guide – try to place the cells in the
• defined area. place the cells in the defined
Fence – must
• Region
area and keep place
– must out allthe
other cells.
cells in the defined
area, but other cells may also be placed
there. 20
 Design
Import
Floorpla
n

Placement Blockages and Halos Placemen

t
CTS
• Placement blockage halos are areas Rout
that the tools should not place any e
Keepout Finish

• cells.
These, too, have several types: margin
Design

• Hard Blockage – no cells can be

placed inside.
• Soft Blockage – cannot be used
during placement, but may be
used during optimization. RAM5
• Partial Blockage – an area with
lower utilization.
• Halo (padding) – an area
outside a macro that should
be kept clear of standard cells. Pins are on
left and
right 21
 Design
Import
Floorpla
n

Placement Blockages and Halos Placemen

t
CTS

Route

Finish

Design
Hard blockage
always created
on all four sides

Soft blockage
created only for the
channels between
the macros or
between the macro
and the core
boundary
22
 Design
Import
Floorpla
n

Routing Blockage Placemen

t
CTS
• Similar to placement blockage, Rout

routing blockage can be e

Finish
Design
defined. (75,95)
• Blockage is
defined for a
given layer.
Routin
g
blockag
e

(20,20)

23
Guidelines for a good
Design
Import
Floorpla
n

floorplan
Single
Use blockage
Placemen
t
CTS
RAMS out of toimprove
large pin
core area the way in the Rout

corner accessibili e
Finis Desig
Large ty
RAM RAM RAM h n

routing 1 2 3

channel
RAM s RAM RAM RAM
Avoid 4 5 6
Standard cells constricti
area
ve
RAM channels
RAM Avoid many
•
pins in the RAM
q narrow RAM 8
channel. 7
PLL MY_SUB_BLOCK Rotate for pin
accessibility

Pins away
from
24
corners
 1 4 5
2 3
Moving to Hierarchical Power
MSV Floorplanning
Physical Design Design Planning

A bit about
Hierarchical
Design
Or how do you deal with a really big chip

2
 Flat vs. Hierarchical
Design
Import
Fullchip Design Floorpla
n

Design Blk 1 Blk 2 Blk 3

Placemen
t
CTS
If the design is too big, partition it into Rout

hierarchies P&R P&R P&R e

Finish
Flo Flo Flo Design
• Advantages
• Faster runtime, less memory needed for w w w
EDA tools Fullchip Timing
• Faster ECO turn-around time &
Verification
• Ability to do design re-use
• Disadvantages I/O Pad
• Much more difficult for fullchip timing IP
closure (ILMs) Macro
• More intensive design planning Block /
• Feedthrough generation
needed: Tile
• Repeater insertion
• Timing constraint
budgeting
2 • etc.
 Design
Import
Floorpla
n

Hierarchical Design – Time Budgeting Placemen

t
CTS
• Chip level constraints must be mapped correctly to block Rout

constraints as I/O
level e
Finish
Design
set_input_delay 1.5 [get_port
constraints IN1]
1.5n IN
s 1

Block
Boundary
• Interface Logic Models (ILMs) help simplify and speed-up
design
A X A X

B Y B Y

Clk

Original Interface Logic Model

2
Netlist
 Design
Import
Floorpla
n

Hierarchical Design – Pin Assignment Placemen

t
CTS
• Pin constraints include parameters, such Rout

as:
• Layers, spacing, size, e
Finish
Design
overlap
• Net groups, pin guides Pins at partition
corners can
• Pins can be assigned: make routing
difficult
• Placement-based
(flightlines)
• Route-based (trial
• route, boundary
Can be used to influence Pin guide 1
crossings).
automatic pin placement of
• Pinparticular
guides net groups Pin guide 2

Partition 28
 Design
Import
Floorpla
n

Hierarchical Design - Feedthrough Placemen

t
CTS
• For channel-less designs or designs with limited channel
Rout
resources e
Finish
Design
Net
I/O 1 IN
Pin Net2
OUT IN

Partition Partition B Pa
A rtit
io
n
Feedthrough C
Candidates

Net Net1 Net1

I/O 1 a b IN
Pin
Net2 Net2a
OUT IN

29
 The Chip Hall of Fame
• Speaking about floorplans, this is one of the
most essential attributes of an FPGA. And it
started with the:
Source:Xilinx
• Ross Freeman, CEO of Xilinx, bet on
Moore’s law
making transistors cheap enough to
“waste”. Source:Xilinx
• Release date: Nov. 1, 1985
• Process: Seiko 2um
• 64 Logic Cells and FFs, 38 I/O pins
• Originally called a “logic cell array”
and programmed logic was drawn by hand.
2017 Inductee to the IEEE Chip Hall of
 1 4 5
2 3
Moving to Hierarchical Power
MSV Floorplanning
Physical Design Design Planning

Power
Planning
 Design
Import
Floorpla
n

Power Consumption and Reliability Placemen

t
CTS
Dynamic IR-Drop /
Rout
Power Voltage e
Average or Droop Finish
Instantaneou Design

s Power
problem
Static Power Fail
(Leakage
Power)
Electromigrati
Power on
density (EM)
Floorplan problem in
+ the Long run
Design of the
grid

32
 Design
Import

IR Drop Floorpla
n
Placemen
t
CTS
• The drop in supply voltage over the length of the supply Rout

line e
Finish
Design
• A resistance matrix of the power grid is constructed
• The average current of each gate is considered
• The matrix is solved for the current at
each node, to determine the IR-drop.
VDD
VDD Pad Ideal voltage
level

Minimu
m
Toleranc
Actual voltage e Level
33
level
 Design
Import
Floorpla
n

Electromigration (EM) Placemen

t
CTS
• Electromigration refers to the gradual displacement of the Rout

metal atoms of a conductor as a result of the current e

Finish
Design
flowing through that conductor.
• Transfer of electron momentum
• Can result in catastrophic failure do to either
• Open : void on a single wire
• Short : bridging between to wires
• Even without open or short,
EM can cause performance degradation
• Increase/decrease in wire RC

34
 Design
Import

Power Distribution More (Wider) Power

Lines:
Floorpla
n
Placemen
t
• Less Static (IR) drop CTS

• Less Dynamic (dI/dt) Rout

e
drop
• Power Distribution Network functions Finish

BUT
Design
• Less Electromigration
• Carry current from pads to transistors on chip
• Maintain stable voltage with low noise
More (Wider) Power
• Provide average and peak power demands Lines:
• Provide current return paths for signals • Fewer (signal)
• Avoid electromigration & self-heating wearout
routing resources
• Consume little chip area and wire (i.e., higher
congestion)
• Easy to lay out

35
 Design
Import
Floorpla
n

Power Distribution Challenge Placemen

t
CTS
• Assume we have a 1mm long power rail in Rout

M1. e
Finish
Design
• Square resistance is given to be 0.1   10 3
m 
what is the resistance of the
R  R L W 
ohm/square 1000
wire?
• If 0.1
we make a 100nm wide rail, 100 109 m
• Now, given a max current of 1mA/1um,
I max  1mA 100nm 
due to Electromigration, what is the IR 1μm
drop when conducting such a current 0.1mA
IRdrop  max  Rwire  104 103 
through this wire? I 100mV
• So what do we do?
• Make the power rails as wide and as thick as
possible!
36
 Hot
Design
Import
Floorpla
n

Spots Placemen
t
CTS
• We generally map the IR drop of a chip using a color Rout

map to e
Finish
Design
highlight “hot spots”, where the IR drop is bad.

Source:
Cadence

Initial IR Drop Mapping After adding a single wire!

3
 Design
Import

Power and Ground Routing Floorpla

n
Placemen
t
CTS
• Each standard cell or macro has power and Rout

ground signals, i.e., VDD (power) and GND e

Finish
Design
(ground)
• They need to be connected as well
• Power/Ground mesh will allow multiple
paths from P/G sources to destinations
• Less series resistance
• Hierarchical power and ground
meshes
from upper metal layers to lower
metal layers
• Multiple vias between layers
3 • You can imagine that they are HUGE
 Design
Import
Floorpla
n

Standard Approaches to Power Routing Placemen

t
CTS
• Power Rout
• Interconnected vertical and horizontal power
Grid e
Finish
bars. Design
• Common on most high-performance designs.
• Often well over half of total metal on upper
thicker VDD/GND
• Dedicated layers used for VDD/GND.
planes.
• Very expensive.
• Only used on Alpha 21264, Dropped on subsequent
Alphas.
• Simplified circuit analysis.
• Some thoughts/trends:
• P/G I/O pad co-optimization with classic physical
design
• Decoupling capacitors to reduce P/G related voltage
drop
4 • Multiple voltage/frequency islands make the P/G
 Design
Import
Floorpla
n

Power Grid Creation Placemen

t
CTS
• Tradeoff IR drop and EM versus routing Rout
Power
resources lines
e
Finish

• •Require
Initial power
powerestimation
budget
Design

• Average current, max current

• Needdensity
to determine Mx Mx
• General grid structure (gating or multi-
voltage?) Mx-1 Mx-1
• Number and location of power pads (per
voltage) Mx-2 Mx-2
• Metal layers to be used
• Width and spacing of straps
• Via stacks versus available routing tracks
• Rings
• Run initial/ no rings
power network analysis to confirm
• Hierarchical block shielding
design Signal routing area
4
 Design
Import
Floorpla
n

Power Grid Creation – Macro Placement Placemen

t
CTS

Route

Finish

Design

Blocks with
the highest
performance
and highest
power
consumption

Close to border
power pads (IR
drop)
Away from each
other
(EM)
41
 Design
Import
Floorpla
n

Summary – Floorplanning in Innovus Placemen

t
CTS
• Floorplanning is very specific to each design and Init Rout

can include many commands, but the general flow Design

e
Finish
Design
is: Specify
Floorplan
• Initialize Design: Place Hard
• Define Verilog netlist, MMMC (timing, SDC, Macros
extraction, etc.), LEF, IO placement Regions &
• Specify floorplan Blockages
• Define floorplan size, aspect ratio, target utilization
• •Place
Absolute
hardormacros
relative placement
• Define halos and blockages around
macros
• Define regions and blockages
• If necessary, define placement
regions and placement blockage
• If necessary, define routing 42
 Design
Import
Floorpla
n

Summary – Floorplanning in Innovus Placemen

t
CTS
• Define Global nets
Init Rout
• Tell the tool what the names of the global nets e
Design Finish
(VDD, GND) are and what their names are in the Design
Specify
IPs.
Floorplan
• Create Power Rings Place Hard
• Often rings for VDD, GND are placed around Macros
the chip periphery, as well as around each Regions &
• individual hard IP. cell ‘follow pins’
Connect standard Blockages
• Build
• BuildPower Grid on metal layers
power stripes Global
• Make sure power connects to hard IPs Nets
• Assign
robustly
Pins Power
• If working on a block (not fullchip), assign Rings
pins to the periphery of the floorplan. Power
Grid
Pin
Assignment 43
 Main References
• IDESA
• Rabaey
• CMOS VLSI
Design
• EPFL Tutorial
• Experience!

44