Digital VLSI

Design

Lecture 5:
Timing
Analysis
 1 2 3 4 5
Sequential Static Timing Design Timing Multi Mode
Clocking Analysis Constraints Reports Multi
Corner

Sequential Clocking
Synchronous Design -
Reminder
•The majority of digital designs are Synchronous
and constructed with Sequential Elements.
• Synchronous design eliminates
races (like a traffic light).
• Pipelining increases throughput.
• We will assume that all
sequentials are
Edge-Triggered, using D-Flip
Flops as registers.
• D-Flip Flops have three critical
timing parameters:
• tcq – clock to output: essentially a
propagation delay
3
• tsetup – setup time: the time the
Timing Parameters - tcq
•tcq is the time from the clock edge until the
data appears at the output.
•The tcq for rising and falling outputs is
different.

clk

tcqLH tcqHL tcqLH

4
 Timing Parameters - tsetup
•tsetup - Setup time is the time the data has to arrive before the
clock
to ensure correct sampling.

clk

tsu tsu tsu

Good! Good! BAD

!
Q

6  Ad
Timing Parameters - thold
•thold - Hold time is the time the data has to be stable after the
clock
to ensure correct sampling.

clk

thold thold thold

Good! Good! BAD

!
Q

6
 Timing Constraints
• There are two main problems that can arise in synchronous
logic:
• Max Delay: The data doesn’t have enough time to
pass from one register to the next before the next
clock edge.
• Min Delay: The data path is so short that it passes
through several registers during the same clock
cycle.

• Max delay violations are a result of a slow

data path, including the registers’ tsetup,
therefore it is often called the “Setup”
path. 7
Setup (Max) Constraint
• Let’s see what makes up our clock cycle:
• After the clock rises, it takes tcq for the data to propagate to
point A.
• Then the data goes through the delay of the logic to get to
point B.
• The data has to arrive at point B, tsetup before the next clock.
• In general, our timing path is a race:
• Between the Data Arrival, starting with the launching clock
clk Logic
edge. D Q
A B
D Q

• And Dthe Data Capture,

tcq one clock period later.
A clk

B
tsetup 8
Setup (Max)
Launch Path
Constraint
margin

positive clock
skew

Capture Path

T  tcq
 tlogic  tsetup
Adding in clock skew and other
guardbands:
 tcq
T  skew  tlogic  tsetup  margin
 Hold (Min) Constraint
•Hold problems occur due to the logic changing before thold has passed.
• This is not a function of cycle time – it is relative to a single clock
edge!
• Let’s see how this can happen:
• The clock rises and the data at A changes after tcq.
• The data at B changes tpd(logic) later.
• Since the data at B had to stay stable for thold after the clock (for
the
clksecond register), the change at B has to be at least thold after
theDclock edge. D Q Logic D Q
A B
tcq
A

B clk
thold
1
Hold (Min)
Constraint Launch Path

margi
n

positive clock
skew
Capture Path

tcq  t 
triggered on same clock
edge!
hold
t
logic
Adding in clock skew and other guardbands:

tcq  tlogic t hold  skew

 Summar
y
• For Setup constraints, the data has to propagate
fast enough to be captured by the next clock tlaunch  T  tcapture
edge:
• This sets our maximum
frequency.
• If we have setup failures, we
T skew  tcq  tlogic  tsetup margin
can always just slow down the
• Forclock.
Hold constraints, the data path delay has
to be long enough so it isn’t accidentally
captured by the same clock edge: tlaunch  tcapture
• This is independent of clock
period.
• If there is a hold failure,
tcq  tlogic margin  thold skew
1
you can throw your chip away!
 1 2 3 4 5
Sequential Static Timing Design Timing Multi Mode
Clocking Analysis Constraints Reports Multi
Corner

Static Timing
Analysis
Or why and how to calculate slack.
 Static Timing Analysis (STA)
• STA checks the worst case propagation of all possible vectors for min/max delays.
• Advantages:
• Much faster than timing-driven, gate-level simulation
• Exhaustive, i.e., every (constrained) timing path is checked.
• Vector generation NOT required
• Disadvantages:
• Proper circuit functionality is NOT checked
• Must define timing
requirements/exceptions (garbage in
 garbage out!)
• Limitations:
• Only useful for synchronous design
• Cannot analyze combinatorial
feedback loops
• e.g., a flip-flop created out of basic logic
gates
• Cannot analyze asynchronous timing
14
issues
Timing Paths
• A path is a route from a Startpoint to an D Q A S D Q
Endpoint.
• Startpoint
• Clock pins
(SP)
of the flip flops Clk Clk
• Input ports , a.k.a Primary
D Q B Co D Q
Inputs (PI)
• Endpoints
• Input pins of the flip
(EP) Clk
Clk
flops
(except the clock pins) D Q Ci
• Output ports, a.k.a
Primary Outputs (PO)
• There can
• Memories / Hard
Clk
• Many paths going to any one endpoint
be:macros
• Many paths for each start-point and end-point
combination

15
Static Timing Analysis
• Four categories of timing
paths • Input to Register
• Register to Register (in2reg)
(reg2reg) • Input to Output
• Register to Output (in2out)
(reg2out)

16
 Goals of Static Timing Analysis
• Verify max delay and min delay constraints are met for all paths in a
design.
• Start with a Gate-Level Netlist.
• Timing Models are provided for every gate in the library.
• Static Timing Analysis needs to report if any path
violates the max/min delay constraints.
• But is this enough?
• No!
• We want to know all the paths that violate the
timing constraints.
• In fact, we want to know the timing of all paths
reported in order of length.
• And we want to know where the problems are so 17
 Some basic assumptions
• Our design is synchronous
• In addition, we will only be showing how to
deal with combinational elements and max
delay constraints.
• We will assume a pin-to-pin delay model
• In other words, each gate has a single,
constant delay from input to output.
• In the real world, gate delay is affected by many factors, such as
gate type, loading, waveform shape, transition direction,
particular pin, and random variation.
• As we saw earlier, a real design gets all this data from the .lib
files.
• We will take a topological approach
• In other words, we disregard the logical functionality of the gates 18
and therefore, consider all paths, though some of them cannot
 Simple path representation
a c
• Let’s say we have the following e
circuit: d
b
• And the timing model of our AND gate
2
is:
• We will build a graph: 2
• Vertices: Wires, 1 per gate a 2
output c 2
• Edges and 1 for
Gates, each
input pinSP
toand
output pin, e
: EP.
1 edge per input with a delay for each b 2
d 2
• Finally, addedge.
Source/Sink Nodes:
• 0-weight edge to each SP and from each EP.
0 a 2
• That way all paths start and end at a single 0 c
2
node. SR b 2 e SN
0
C 0 2 K
2 dam Teman, 2018
 Node oriented timing analysis
• If we would enumerate every path, we would quickly get
exponential explosion in the number of paths.
• Instead, we will use node-oriented timing analysis
• For each node, find the worst delay to the node along any path.
• For this, we need to define two important values:
• Arrival Time at a node (AT): the longest path from the source to the
node.
• Required Arrival Time at node (RAT): the latest time the signal
is allowed to leave the node to make it to the sink in time.
Slack at node n is defined
as:
Slack(n) = RAT(n) – AT(n)
20
 How do we compute ATs and RATs?
• Recursively!
• The Arrival Time at a node is just the maximum of
the ATs at the predecessor nodes plus the delay from that
node.
• The Required Arrival Time to a node is just the
minimum of the RATs at the successor nodes minus the
delay to that node.  0 n
SRC
AT n   max AT p   p,
  
  n
ppredn SRC
n   T n
SNK
RATn   min RAT s   n,
ssuccn    n
 SNK
s 21
 So let’s try to understand AT, RAT, and
Slack If the signal arrives too late,
we get negative slack, which
means there is a timing
violation.

Slac Slack
k RAT(n
AT(n RAT(n )
AT(n
) ) RAT: longest
AT: )
logic delay to the
longest capture edge of
logic the clock
delay (dependent on
after cycle time)
launch of
clock Launc Clock cycle time Captur Clock cycle time
h (T) e (T)

22
 Now let’s see an example
• Just look at this path and try to find the worst
path.
• Does it meet a cycle time of T=12
3 ?g
a 1 2
d 5 1
4 f j
3
1 2 k
b 4
c 3 h
2 5 n
e
• Now let’s fill in the RAT, AT, and SLACK of each node
and:
• Quickly find out if we meet timing
• Figure out what the worst path is
23
 Now let’s see an example
• We’ll start by representing it as a
directed acyclic graph (DAG)
• Next, we’ll compute ATs from SRC to
SNK
0 1 4 7
1 3 2
a g j
0 d 5 1 0
0 0 6 12 15
0 4 3 0
SR
b f 4 k SN
C
2 K

0 1 h
0 2 3 15 0
5
2 10
c e n
24
 Now let’s see an example
• And now RAT from SNK to
SRC

0 -3 1 -2 4 10 7 12
1 3 2
a d g j
0 5 1 0
0 -3 0 -1 6 3 12 12 15 12
0 4 3 0
SR
b f 4 k SN
C
2 K

0 1 h
0 2 2 4 3 15 12 0
5
2 10 7
c e n
25
 Now let’s see an example
• And finally, we can calculate the slack.
• And guess what – we found the critical
path!
0 -3 -3 1 -2 -3 4 10 6 7 12 5
1 3 2
a d g j
0 5 1 0
0 -3 -3 0 -1 -1 6 3 - 12 12 15 12 -3
0 4 3 3 0 0
SR
b f 4 k SN
C
2 K

0 1 h
0 2 2 2 4 2 3 5 15 12 -3 0
2 10 7 -3
c e n
26
 False Paths
• We saw how to find the RAT, AT and Slack at every node.
• All of this can be done very efficiently and be adapted for
min timing, sequential elements, latch-based timing, etc.
• Even better, we can quickly report the order of the critical
paths.
• However, thiswhy
• Let’s see wasthis
all done
is a topologically (i.e., without looking at
This is called a “False
logic).
problem Path”
8 2 8 8
a d g 2 a 2 8 g 2
0 0
f 1 2 j d
1 1 1 2 1
b e h 1
2 b 2 h
e
1 1 1 1
c i c
2  Adam Teman, 2018