AMBA AXI Protocol

Advanced eXtensible Interface

 The Advanced eXtensible Interface
(AXI)
AXI is an on-chip communication bus protocol developed by
ARM
AMBA AMBA AMBA
3 4 5
AXI4

AXI3 AXI4-Lite AXI5

AXI4-stream

2003 2010 2013

AXI is targeted at high performance and frequency systems designs.

 Burst-Based transactions with only one
address

Supports unaligned data-transfer (Strobes)

Separate the read and write data

AXI channels

Features Supports optional low-power operation

Ability to issue multiple outstanding address and

out-of-order transaction completion

Separate the address phase from the data phase

Architecture
AXI Protocol system
Master 1 Master 2 Master 3

Interface

Interconnect

Interface

Slave 1 Slave 2 Slave 3 Slave 4

AXI provides a single interface definitions for all the possible

connections of the system
 AXI Master-Slave Connection
Each Channel has:
- Information signals.
- Valid and Ready handshake.
 Address Channels: Carries
address and control information.
 Read Data Channel: Transfers
both read data and info
from the slave.
 Write Data Channel:
Transfers
write data to the slave.
 Write response Channel:
Slave respond to
the write transactions
Signals
 Global Signals

Signal Source Description

ACLK Clock source Global clock signal. All signals are sampled on the rising edge of the global clock.
ARESET Reset source Global reset signal. This signal is active LOW.
n
 Write address channel signals
Signal Source Description
AWID[3:0] Master Write address ID. This signal is the identification tag for the write address group of signals
AWADDR[31:0]. Master Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control
signals are used to determine the addresses of the remaining transfers in the burst.

AWLEN[3:0] Master Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data
transfers associated with the address.
AWSIZE[2:0] Master Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.

AWBURST[1:0] Master Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated

AWLOCK[1:0] Master Lock type. This signal provides additional information about the atomic characteristics of the transfer.

AWCACHE[3:0] Master Cache type. This signal indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.

AWPROT[2:0] Master Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the
transaction is a data access or an instruction access.
AWVALID Master Write address valid. This signal indicates that valid write address and control information are available: 1 = address and control
information available 0 = address and control information not available. The address and control information remain stable until the
address acknowledge signal, AWREADY, goes HIGH.

AWREADY Slave Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals: 1 = slave ready
0 = slave not ready.
 Write data channel signals

Signal Source Description

WID[3:0] Master Write ID tag. This signal is the ID tag of the write data transfer. The WID value must match the AWID value of
the write transaction.
WDATA[31:0] Master Write data. The write data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide.
WSTRB[3:0] Master Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight
bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) +7:(8 × n)].
WLAST Master Write last. This signal indicates the last transfer in a write burst.
WVALID Master Write valid. This signal indicates that valid write data and strobes are available: 1 = write data and strobes
available 0 = write data and strobes not available.
WREADY Slave Write ready. This signal indicates that the slave can accept the write data: 1 = slave ready 0 = slave not ready.
 Write response channel signals

Signal Source Description

BID[3:0] Slave Response ID. The identification tag of the write response. The BID value must match the AWID
value of the write transaction to which the slave is responding.

BRESP[1:0] Slave Write response. This signal indicates the status of the write transaction. The allowable responses
are OKAY, EXOKAY, SLVERR, and DECERR.

BVALID Slave Write response valid. This signal indicates that a valid write response is available: 1 = write
response available 0 = write response not available.
BREADY Master Response ready. This signal indicates that the master can accept the response information. 1 =
master ready 0 = master not ready.
 Read address channel signals
Signal Source Description

ARID[3:0] Master Read address ID. This signal is the identification tag for the read address group of signals.

ARADDR[31:0] Master Read address. The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is
provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining
transfers in the burst
ARLEN[3:0] Master Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data
transfers associated with the address
ARSIZE[2:0] Master Burst size. This signal indicates the size of each transfer in the burst.

ARBURST[1:0] Master Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is
calculated.
ARLOCK[1:0] Master Lock type. This signal provides additional information about the atomic characteristics of the transfer.

ARCACHE[3:0] Master Cache type. This signal provides additional information about the cacheable characteristics of the transfer.

ARPROT[2:0] Master Protection type. This signal provides protection unit information for the transaction

ARVALID Master Read address valid. This signal indicates, when HIGH, that the read address and control information is valid and will remain
stable until the address acknowledge signal, ARREADY, is high. 1 = address and control information valid 0 = address and
control information not valid
ARREADY Slave Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals: 1 = slave
ready 0 = slave not ready.
 Read data channel signals

Signal Source Description

RID[3:0] Slave Read ID tag. This signal is the ID tag of the read data group of signals. The RID value is generated by the slave
and must match the ARID value of the read transaction to which it is responding.
RDATA[31:0] Slave Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide.

RRESP[1:0] Slave Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY,
EXOKAY, SLVERR, and DECERR.
RLAST Slave Read last. This signal indicates the last transfer in a read burst.

RVALID Slave Read valid. This signal indicates that the required read data is available and the read transfer can complete: 1 =
read data available 0 = read data not available.
RREADY Master Read ready. This signal indicates that the master can accept the read data and response information: 1= master
ready 0 = master not ready.
Write Transaction
Read Transaction
Burst Types and Addressing

Burst Types
A burst is a sequence of data transfers following a single address phase. AXI supports the following burst types:
1. FIXED (00)
 Address: Remains constant for every data transfer.
 Use Case: Useful for accessing peripherals like FIFOs.
 Example: All data beats are sent to the same address.
2. INCR (01)
 Address: Increments by the size of each data beat.
 Use Case: Common for memory-mapped data transfers.
 Example: Transfers data from or to a memory array.
3. WRAP (10)
 Address: Increments like INCR but wraps around at a boundary aligned to the burst length.
 Use Case: Cache line fills.
 Example: For a 4-beat burst of 4 bytes each, addresses wrap at 16 bytes.
 Addressing in Bursts

🔹 Start Address: Provided in the address phase. Determines the location of the first data transfer.

🔹 Burst Length (AxLEN): Number of transfers in the burst (0–255, where actual transfers = AxLEN + 1).

🔹 Burst Size (AxSIZE): Number of bytes per transfer (e.g., 1 = 2 bytes, 2 = 4 bytes, etc.).

🔹 Total Bytes Transferred = (AxLEN + 1) × 2^AxSIZE

Example

Given:
 AxBURST = INCR
 AxLEN = 3 (so 4 transfers)
 AxSIZE = 2 (each beat = 4 bytes)
 Start Address = 0x1000

• Resulting Addresses:
0x1000, 0x1004, 0x1008, 0x100C
 QoS and ID-based transactions

QoS (Quality of Service)

Purpose: QoS helps prioritize transactions to ensure that time-critical data is serviced first.

Signal: AWQOS / ARQOS (4-bit signals):

o Sent during the write (AWQOS) or read (ARQOS) address phase.

o Indicates the priority level of a transaction.

Implementation:

 Optional in AXI systems.

 Slaves and interconnects can use the QoS value to schedule or arbitrate requests.
ID-Based Transactions
Purpose: Supports out-of-order completion and multiple outstanding transactions from the same master.

Signals Involved:
 AWID / ARID: Transaction ID during write/read address phase.
 WID (AXI3 only): Write data ID (merged with AWID in AXI4).
 BID / RID: Returned by slave to identify which transaction a response belongs to.

Benefits:
 Allows pipelining and overlapping of transactions.

Example

System: A multi-master system with a CPU, GPU, and DMA controller.

 CPU sends a low-latency, high-priority read with ARQOS = 0xF and ARID = 0x1.
 DMA controller sends a bulk write with AWQOS = 0x1 and AWID = 0x5.

Result:
 The interconnect grants higher priority to the CPU's read.
 The slave responds with RID = 0x1, so the CPU knows the response is for its request.
 AXI4 Lite

Five channels make up the AXI4-Lite interface: Write Address, Write Data, Write Response, Read Address, and Read Address.
The key features of AXI4 lite are
• Each transaction burst length is 1.
• data bus width is 32 bits or 64 bits and all transactions are the same width as the data bus.
• All accesses are non – modifiable and non- bufferable hence AxCACHE is 0000.
Feature / Aspect AXI4 (Full) AXI4-Lite

Burst Transfers Supported (INCR, FIXED, WRAP bursts) Not supported (only single data transfer)

Maximum Burst Length 1 to 256 data beats Always 1 data beat

ID Support Multiple outstanding transactions No ID support, one transaction at a time

Out-of-Order Support Yes (with IDs) No, strictly ordered

Cache & QoS Signaling Supported Not present

Address Width Typically 32 or 64 bits Typically 32 bits

Data Width 32 / 64 / 128 / 256 bits, etc. Usually 32 or 64 bits

Use Case High-throughput memory and data streaming Control and status register access

Slave Interface Complexity High Low

Resource Usage High (more logic and routing) Low (minimal logic)

Performance High Low to moderate

Protocol Channels 5 independent channels Same 5 channels, but simplified

 AXI-Stream protocol

• The AXI-Stream protocol is used as a standard interface to exchange data between connected
components. AXI-Stream is a point-to-point protocol, connecting a single Transmitter and a single
Receiver.
 Signal list
Signal Source Width Description

ACLK Clock 1 ACLK is a global clock signal. All signals are sampled on the rising edge of ACLK.

ARESETn Reset 1 ARESETn is a global reset signal.

TVALID Transmitter 1 TVALID indicates the Transmitter is driving a valid transfer. A transfer takes place when both
TVALID and TREADY are asserted.

TREADY Receiver 1 TREADY indicates that a Receiver can accept a transfer.

TDATA Transmitter TDATA_WIDTH TDATA is the primary payload used to provide the data that is passing across the interface.
TDATA_WIDTH must be an integer number of bytes and is recommended to be 8, 16, 32, 64, 128,
256, 512 or 1024-bits.
TSTRB Transmitter TDATA_WIDTH/8 TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is
processed as a data byte or a position byte.
TKEEP Transmitter TDATA_WIDTH/8 TKEEP is the byte qualifier that indicates whether content of the associated byte of TDATA is
processed as part of the data stream.
TLAST Transmitter 1 TLAST indicates the boundary of a packet.

TID Transmitter TID_WIDTH TID is a data stream identifier. TID_WIDTH is recommended to be no more than 8.

TDEST Transmitter TDEST_WIDTH TDEST provides routing information for the data stream. TDEST_WIDTH is recommended to be
no more than 8.
TUSER Transmitter TUSER_WIDTH TUSER is a user-defined sideband information that can be transmitted along the data stream.
TUSER_WIDTH is recommended to be an integer multiple of TDATA_WIDTH/8.
 Common AXI violations

1. Handshake Violations
 Missing VALID/READY handshake: One side asserts VALID without the other side asserting READY, and does not hold it until handshake
completes.
 Premature deassertion of VALID: VALID is deasserted before READY goes high.
 READY toggle without VALID: READY toggles unnecessarily when VALID is low.

2. Address Violations
 Unaligned address access: For burst transfers, addresses must be aligned with data size (e.g., 4-byte data should be 4-byte aligned).
 Changing address during burst: Address should remain stable during a burst.

3. Burst Violations
 Incorrect burst length (ARLEN / AWLEN): Using invalid values (e.g., 0 for a burst when 1 or more is expected).
 Burst type violations: Using unsupported BURST types like WRAP when not handled.
 Crossing 4KB boundary: AXI does not allow bursts to cross 4KB address boundaries.
4. Response Violations
 Missing response (BRESP, RRESP): Responses must be sent even for dropped transactions.
 Invalid response code: Sending a reserved or undefined value in RESP.

5. Out-of-order and ID handling

 Mismatched IDs: Response ID (RID, BID) does not match the request ID (ARID, AWID).
 Illegal interleaving: Transactions with the same ID are issued before the first one completes.
 Unsupported out-of-order responses: If the slave does not support reordering, master must comply.

6. Data Violations
 Data beats mismatch: WLAST or RLAST is missing or asserted at wrong time.
 Changing control signals during data: WSTRB, WDATA, or WVALID change before handshake completes.

8. Reset Handling
 Signal assertion during reset: Driving VALID or other active signals when ARESETn is low.