EE203 Digital System

Design

Lecture18. Sequential Circuit Design

[Chap. 16]
May 25, 2006

EE203 Digital System Design

 Objectives

1. Design a sequential circuit using gates and flip-flops.

2. Test your circuit by simulating it and by implementing it in lab.
3. Design a unilateral iterative circuit. Explain the relationship
between iterative and sequential circuit, and convert from one to
the other.
4. Show how to implement a sequential circuit using a ROM or PLA
and flip-flops.
5. Explain the operation of CPLDs and FPGAs and show how they
can be used to implement sequential logic.

EE203 Digital System Design

 Summary of Design Procedure for Sequential Circuits

1. Given the problem Statement, determine the relationship between the input and output
sequences and derive state table. Construct a State Graph.

2. Reduce the table to a minimum number of states. Eliminate duplicates rows by row matching
and then form an implication table.

3. Use Flip/flops for representing states. Assign a unique combination of F/F states corresponds
to in each state in reduced table.

4. Form a transition table.

5. Plot next-state map and input maps for F/F and derive the input F/F equations.

6. Realize the F/F input equations and output equations using available logic

7. Testing your circuit 3

EE203 Digital System Design

16.2 Design Example-Code Converter

BCD code  excess 3 code converter

X Z
INPUT OUTPUT
(BCD) (excess-3)

TABLE 16-1

t3 t2 t1 t0 t3 t2 t1 t0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0 4

EE203 Digital System Design

16.2 Design Example-Code Converter

INPUT Sequence Received Present Next State Present Output(Z)

TIME (Least significant Bit First) State X = 0 1 X = 0 1

t0 reset A B C 1 0
t1 0 B D F 1 0
1 C E G 0 1
00 D H L 0 1
t2 01 E I M 1 0
10 F J N 1 0
11 G K P 1 0
000 H A A 0 1
001 I A A 0 1
010 J A - 0 -
t3 011 K A - 0 -
100 L A - 0 -
101 M A - 1 -
110 N A - 1 -
111 P A - 1 -
5

EE203 Digital System Design

16.2 Design Example-Code Converter

TABLE16-3 Reduced State Table for Code

Converter
Next Present
Present State Output(Z)
Time State X = 0 1 X = 0 1
t0 A B C 1 0

t1 B D E 1 0
C E E 0 1
t2 D H H 0 1
E H M 1 0
t3 H A A 0 1
M A - 1 -

6
H I  J K L , M  N P and E F G
EE203 Digital System Design
16.2 Design Example-Code Converter

Figure 16-1: State Graph for Code

Converter

EE203 Digital System Design

16.2 Design Example-Code Converter

Figure 16-2: Assignment Map for Flip

Flops

Z
Q1 Q2 Q3
Q1Q2 Q3 X=0 X=1 X=0 X=1
A 000 100 101 1 0
B 100 111 110 1 0
C 101 110 110 0 1
D 111 011 011 0 1
E 110 011 010 1 0
H 011 000 000 0 1
M 010 000 xxx 1 x
- 001 xxx xxx x x

8
(b)transition tableEE203 Digital System Design
16.2 Design Example-Code Converter

Figure 16-3: Karnaugh Maps for Code Converter Des

ign

After the state assignment has

been made the transition table is
filled in according to the
assignment, and the next-state
maps are plotted as shown in
Figure 16-3

EE203 Digital System Design

16.2 Design Example-Code Converter

Figure 16-4: Code Converter

Circuit

Figure 16-4 shows the resulting sequential 10

circuit EE203 Digital System Design
 16.3 Design of Iterative Circuits

Sequential Circuit Design  Iterative Design

Figure 16-5: Unilateral Iterative

Circuit

The simplest form of an iterative circuit consists of a linear array of

combinational cells with signals between cells traveling in only one 11
direction. EE203 Digital System Design
 16.3 Design of Iterative Circuits

Comparator Design using Iterative Circuit

Figure 16-6: Form of Iterative Circuit for Comparing Binary

Numbers

Figure 16-6 shows the form of the iterative circuit, although the
number of leads between each pair of cells is not yet know.
12

EE203 Digital System Design

16.3 Design of Iterative Circuits

TABLE 16-4 State Table for

Comparator

Si+1
Si XiYi = 00 01 11 Z1 Z2 Z3
10
X=Y S0 S0 S2 S0 S1 0 1 0

X>Y S1 S1 S1 S1 S1 0 0 1

X<Y S2 S2 S2 S2 S2 1 0 0

13

EE203 Digital System Design

16.3 Design of Iterative Circuits

TABLE 16-5 State Assignment and Transition Table for Comparator

ai bi xiyi= 00 01 11 10 Z1 Z2 Z3

0 0 00 10 00 01 0 1 0

0 1 01 01 01 01 0 0 1

1 0 10 10 10 10 1 0 0

Equations for the first cell

(a1=b1=’00’)

14

EE203 Digital System Design

16.3 Design of Iterative Circuits

Figure 16-7:Typical Cell for

Comparator

15

EE203 Digital System Design

16.3 Design of Iterative Circuits

Figure 16-8: Output Circuit for

Comparator
output maps, equations, and circuit.

16
Z1 =1 if X < Y , Z2=1 if X = Y , Z3=1 if X > Y
EE203 Digital System Design
16.3 Design of Iterative Circuits

Figure 16-9: Sequential Comparator for Binary

Numbers

17
Figure 16-9 shows the resulting
circuit. EE203 Digital System Design
 16.4 Design of Sequential Circuits Using ROMs and PLAs

equential Circuit can be designed using a ROM and F/F’s

(a)State
table
Present Next State Present Output (Z)
State X= 0 1 X= 0 1

A B C 1 0

B D E 1 0
C E E 0 1
D H H 0 1
E H M 1 0
H A A 0 1
M A - 1 -

18

EE203 Digital System Design

16.4 Design of Sequential Circuits Using ROMs and PLAs

TABLE 16-6 (b)Transition table

   Z
Q1 Q2 Q3
Q1 Q2 Q3 X=0 X=1 X=0 X=1

A 0 0 0 001 010 1 0
B 0 0 1 011 100 1 0
C 0 1 0 100 100 0 1
D 0 1 1 101 101 0 1
E 1 0 0 101 110 1 0
H 1 0 1 000 000 0 1
K 1 1 0 000 - 1 -

D1 Q1 , D2 Q2 and D3 Q3 19

EE203 Digital System Design

16.4 Design of Sequential Circuits Using ROMs and PLAs

X Q1 Q2 Q3 Z D1 D2 D3
TABLE 16-6
0 0 0 0 1 0 0 1
(c)Truth table 0 0 0 1 1 0 1 1
0 0 1 0 0 1 0 0
0 0 1 1 0 1 0 1
*ROM INPUTS
0 1 0 0 1 1 0 1
(X,Q1,Q3 and Q3) 0 1 0 1 0 0 0 0
0 1 1 0 1 0 0 0
*ROM 0 1 1 1 x x x x
OUTPUTS 1 0 0 0 0 0 1 0
(Z,D1,D2 and 1 0 0 1 0 1 0 0
D3) 1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 0 1 1 0
1 1 0 1 1 0 0 0
1 1 1 0 x x x x 20
1 1 1 1 x x
EE203 x SystemxDesign
Digital
16.4 Design of Sequential Circuits Using ROMs and PLAs

Figure 16-10:Realization of Table 16.6(a) Using a

ROM

A ROM with four input(24

words) and four outputs is
required, as shown in
Figure16-10
21

EE203 Digital System Design

16.4 Design of Sequential Circuits Using ROMs and PLAs

D1 Q1 Q2'
D2 Q2 Q1
D3 Q3 Q1Q2Q3  X 'Q1Q3'  XQ1'Q2'
Z  X 'Q3'  XQ3

TABLE 16-7 X Q1 Q2 Q3 Z D1 D2 D3

- - 0 - 0 1 0 0
- 1 - - 0 0 1 0
- 1 1 1 0 0 0 1
0 1 - 0 0 0 0 1
1 0 0 - 0 0 0 1
0 - - 0 1 0 0 0
1 - - 1 1 0 0 0
22

EE203 Digital System Design

16.4 Design of Sequential Circuits Using ROMs and PLAs

Figure 16-11: Segment of Sequential

PAL

Q  D  A' BQ '  AB 'Q 23

EE203 Digital System Design

16.5 Sequential Circuit Design Using CPLDs

Figure 16-12: CoolRunner-II Architecture(Figure based on figures and text owned by X

ilinx, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc. 1999-2003. All rights reserved.)

Figure 16-12 shows the structure of a Xilinx CoolRunner II CPLD, w 24

hich uses a PLA in each function block.
EE203 Digital System Design
16.5 Sequential Circuit Design Using CPLDs

Figure 16-13: CoolRunner-II Macrocell(Figure based on figures and text owned by Xilin
x, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc. 1999-2003. All rights reserved.)

Figure 16-13 represents a

CoolRunner-II macrocell an 25
d the associated AND array.
EE203 Digital System Design
16.5 Sequential Circuit Design Using CPLDs

Figure 16-14: CPLD Implementation of a Mealy

Machine

Figure 16-14 shows how

a Mealy sequential
machine with two input,
two outputs, and two
flip-flops can be 26
implemented by a CPLD
EE203 Digital System Design
16.5 Sequential Circuit Design Using CPLDs

Figure 16-15: CPLD Implementation of a Shift

Register

Figure 16-15 shows how

the 4-bit loadable right-s
hift register of Figure 12-
15 can be implemented u
sing four macrocells of a
CPLD 27

EE203 Digital System Design

16.5 Sequential Circuit Design Using CPLDs

Figure 16-16: CPLD Implementation of a Parallel Adder with

Accumulator
X i  X i  Yi  ci
T INPUT is
Ti  X i  X i Yi  Ci

Figure 16-16 shows how three

bit of the parallel adder with
accumulator of Figure 12-5 can
be implemented using a CPLD.

28

EE203 Digital System Design

16.6 Sequential Circuit Design Using FPGAs

Figure 16-17: Xilinx Virtex/Spartan II CL

B (Figure based on figures and text owned by Xilinx, Inc., C
ourtesy of Xilinx, Inc. © Xilinx, Inc.1999-2003. All rights rese
rved.)

29

EE203 Digital System Design

16.6 Sequential Circuit Design Using FPGAs

Figure 16-18: FPGA Implementation of a Mealy

Machine

Figure 16-18 shows how a Mealy

sequential machine with two
inputs, two output, and two flip-
flops can be implemented by a
FPGA.

30

EE203 Digital System Design

16.6 Sequential Circuit Design Using FPGAs

Figure 16-19: FPGA Implementation of a Shift

Register

*Figure 16-19 shows how

the 4-bit loadable right-
shift register Figure 12-15
can be implemented using
an FPGA.

Q3 CE 'Q3  CED3 f ( Ld  Sh)( Sh ' D3  ShSI )

D3 f is the D input to flip  flop3 therefore
31
D3 f Sh ' D3  ShSI
EE203 Digital System Design
16.6 Sequential Circuit Design Using FPGAs

Figure 16-20: FPGA Implementation of a Parallel Adder with

Accumulator

Figure 16-20 shows how three bits

of the parallel adder with
accumulator of Figure 12-5 can be
32
implemented using an FPGA
EE203 Digital System Design
16.7 Simulation and Testing of Sequential Circuits

Figure 16-21: Simulator Output for an

Inverter

Figure 16-21 shows the output from an inverter

which has a nominal delay of 10 ns, a minimum 33
delay of 5 ns, and a maximum delay of 15EE203
ns. Digital System Design
16.7 Simulation and Testing of Sequential Circuits

Figure 16-22: Simulation Screen for Figure

13-7

Figure 16-22 shows a simulator screen

for testing the Mealy sequential circuit
34
of Figure 13-7.
EE203 Digital System Design
16.7 Simulation and Testing of Sequential Circuits

Figure 16-23

Figure 16-23 shows the simulator

input waveform for the example
of Figure 16-22,using the test
sequence X=10101.
35

EE203 Digital System Design

16.7 Simulation and Testing of Sequential Circuits

Figure 16-24: Using a Shift Register to Generate Synchronized

Inputs

The former can be accomplished by loading the inputs

into a shift register, and then using the circuit clock to
shift them into the circuit one at a time, as shown in figure
16-24.
36

EE203 Digital System Design

16.7 Simulation and Testing of Sequential Circuits

Figure 16-25

37

EE203 Digital System Design

16.7 Simulation and Testing of Sequential Circuits

Figure 16-26: Synchronizer with Two D Flip-Flops

Figure 16-26 shows a more

reliable synchronizer that
uses two D flip-flop to
synchronize a single
asynchronous input,X

38

EE203 Digital System Design

16.7 Overview of Computer-Aided Design

Functions performance of CAD tools

•Generation and Minimization of logic equation

•Generation of bit patterns for programming PLD’s
•Schematic Capture
•Simulation
•Synthesis tools
•IC design and Layout
•Test Generation
•PC board Layout

39

EE203 Digital System Design

16.7 Simulation and Testing of Sequential Circuits

Design a small digital systems with an FPGA

1. Draw a block diagram of the digital system. Define the

required control signals and construct state graph and
describes the required sequence of operations
2. Workout a detailed logic design using gates,
F/F,register, counter,adders, etc… (HDL)
3. Construct a logic diagram using a schematic capture
program(HDL)
4. Simulate and debug the logic diagram and make any
necessary corrections to the design(HDL)
5. Run an implementation program that fits the design into
the target FPGA
40
6. Simulation and verifying
EE203 Digital System Design
7. Download the bit pattern into FPGA and test.