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Timing Verification

The document discusses the importance of timing verification in VLSI circuit design, highlighting the challenges posed by technology trends such as increased capacitive and inductive coupling. It outlines the design flow, including post-synthesis and post-layout verification processes, and emphasizes the need for accurate timing analysis to ensure circuits meet timing constraints. The conclusion stresses that timing verification is critical for the design cycle and impacts time to market for next-generation VLSI circuits.

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Lakshmisree Sajit
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12 views24 pages

Timing Verification

The document discusses the importance of timing verification in VLSI circuit design, highlighting the challenges posed by technology trends such as increased capacitive and inductive coupling. It outlines the design flow, including post-synthesis and post-layout verification processes, and emphasizes the need for accurate timing analysis to ensure circuits meet timing constraints. The conclusion stresses that timing verification is critical for the design cycle and impacts time to market for next-generation VLSI circuits.

Uploaded by

Lakshmisree Sajit
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Timing Verification of VLSI

Circuits

Professor Weiping Shi


http://ece.tamu.edu/~wshi/689.html

05/01/25 ELEN 689 1


I. Introduction
 What is EDA?
 Technology trend
 Design flow
 Timing verification flow

05/01/25 ELEN 689 2


Technology Trend
 International Technology
Roadmap for Semiconductors
(ITRS)
 World-wide and industry-wide
cooperation since 1992
 Consensus on R&D needs out to
a 15 year horizon

05/01/25 ELEN 689 3


ITRS Trend for Scaling
Production 200 200 200 200 200 200
year
2 3 4 5 6 7
MPU half- 130 107 90 80 70 65
pitch (nm)
MPU Gate 75 65 53 45 40 35
length
(nm)
Clock 2.3 3.1 4.0 5.2 5.6 6.7
(GHz)
Metal 8 8 8 9 9 9
layers
Supply 1.0 1.0 1.0 0.9 0.9 0.7
05/01/25 ELEN 689 4
voltage
Implication
 Signal propagation becomes
more difficult due to increasing
capacitive and inductive coupling
 Signal integrity degrades and
cause both timing uncertainty
and potential logic errors

05/01/25 ELEN 689 5


Implication
 Testing
 Decreasing pin/gate ratio
 Delay fault v.s. stack-at fault
 Low power
 Heat already a big problem
 Wireless applications
 More…

05/01/25 ELEN 689 6


MPU/ASIC Design Flow
Design Spec

Behavioral
Design Verify Function

Logic Verify Function


Synthesis

Physical Verify Timing


Synthesis and Function

05/01/25 ELEN 689 7


Timing Verification
 Synthesized circuits meet timing
constraints
 Post-synthesis verification

Use simple estimation such as unit delay
 Post-layout verification

Use accurate interconnect and gate
parasitic
 Design closure

05/01/25 ELEN 689 8


Design Closure
Number of Paths Bad
Violating Timing Timing Verification
Constraints

Good
Timing Verification

Iterations

05/01/25 ELEN 689 9


What to Verify?
 Synchronous circuit and scan
design
 Combinational circuit between flip-
flops
 Setup time, hold time, clock skew,
etc Combinational
…

…
Circuit

clock
05/01/25 ELEN 689 10
Setup Time Violation
 Setup time constraint of a flip-flop
specifies a time interval before the
active edge of clock
 Data must arrive before the
interval Clock
Data
Data OK
Clock
Data Violation

05/01/25 ELEN 689 11


Hold Time Violation
 Hold time constraint of a flip-flop
specifies an interval after the
active edge of clock
 Data must be stable in the interval
Clock
Data
Data
Clock Violation

Data OK

05/01/25 ELEN 689 12


Clock Skew
 Signal skew is the arriving time
difference between two signals
 Clock skew between any two
leaves must be within the
requirement

05/01/25 ELEN 689 13


Timing Verification Flow
Layout
Netlist Cell Library
(gds2, LEF/DEF)

Interconnect Parasitic Extraction

Model Order Reduction

Delay Evaluation

Paths Violate
Timing Analysis
Timing Constrains

05/01/25 ELEN 689 14


Example
a

b
XOR NAND NAND
Layout a y
Synthesis

05/01/25 ELEN 689 15


Step 1. Parasitic Extraction
s1
s2
XOR NAND NAND
a Distributed RC
R1 R2 R3 : parasitic
res
C1 C2 C3 : parasitic
R1 cap C
Cxor R2 R3 nand
a s1 Cxor Cnand
s2: gate sink
cap
Parasitic
Extraction C1 C2 C3
or each net

05/01/25 ELEN 689 16


Step 2. Model Order
Reduction
s1
s2
R1 Cxor R2 R3 Cnand
a s1 s2 transfer
functions
C1 C2 C3 h1 s1

h2 s2

a
 load
Model Order
Reduction

05/01/25 ELEN 689 17


Step 3. Delay Evaluation
50% buffer-to-buffer
Buffer-to-buffer Delay: delay at s1
Time for signal to travel
from input pin of a gate h1 s1
to input pin of next gate

h2 s2
a
50% buffer-to-buffer
delay at s2

05/01/25 ELEN 689 18


Step 4. Timing Verification
 Dynamic
 Input vector based
 Expensive when circuit is large
 Static
 Independent of input vectors
 Critical path search
 Fast, but may overestimate

05/01/25 ELEN 689 19


Signal Coupling

Coupling Capacitance
Noise

05/01/25 ELEN 689 20


Crosstalk
 Cross talk affects delay
01
nominal delay
0

01
delay increased
10

01

delay reduced
01

05/01/25 ELEN 689 21


Verification and Testing
 Timing verification identifies paths
that violate timing constraints
 Timing verification also identifies
paths are likely violations
 A near violation can be a true violation
under combination of defects, process
variations and signal coupling
 Delay fault testing

05/01/25 ELEN 689 22


Conclusion
 Technology trend decides important
and urgent areas of research
 Timing verification is a central part
of design cycle, and directly affects
design cycle and time to market
 Timing verification for next
generation VLSI circuits is
increasingly important
05/01/25 ELEN 689 23
Assignments #1
 Read ITRS (http://public.itrs.net/)
and for the area of your interest,
identify issues that are important
 Go to MOSIS (
http://www.mosis.com) and check
their technology file, SPICE models
and design rules

05/01/25 ELEN 689 24

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