Logic Built-in Self

Test (BIST)

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 Introducti
on
• What are the problems in today’s
semiconductor testing?
▪Traditional test techniques
become quite expensive
▪No longer provide sufficiently
high fault coverage

• Why do we need built-in self-test

(BIST)?
▪For mission-critical applications
▪Detect un-modeled faults
▪Provide remote diagnosis
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 BIST

• It is a design technique in which

additional circuits are added to the
functional blocks which enable testing of
the circuit by itself

• It is a combination of the concepts of

built-in test and self-test.

• By using the concept of BIST, there

is a great reduction in the testing
time.
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BIST

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 BIST Vs
● ATE ATE
○ Highly sophisticated high end equipment
○ May not be needed all the time
● Alternative can be software tests for the field
test/diagnosis
○ Low hardware fault coverage
○ Time consuming

● Advantages to go in hardware
○ Lower system test efforts
○ Improved system maintenance and repair
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 Logic Built-In Self-
Test
• TPG
– Constructed from linear feedback shift
register (LFSR) or cellular automata
– Exhaustive testing– all possible 2n test
patterns
– Pseudo-random testing– a subset of 2n
test patterns
– Pseudo-exhaustive testing
• ORA
– Constructed from multiple-input
signature register (MISR)
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BIST
Architecture

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 Types of
• BIST
There are broadly two methods of carrying BIST:
– Online BIST
• Concurrent BIST
• Non-concurrent BIST
– Offline BIST
• Functional BIST
• Structural BIST

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 Online
BIST
• In online BIST, the circuit may be made to
test itself without being disconnected from
the system.

• Concurrent online BIST: Allowing the

testing to be carried out while the circuit
performs its normal operation.

• Non-concurrent online BIST: Normal operation

is put off and only the testing would be
carried out. The test process can be
interrupted any time so that the normal
operation can resume.
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 Offline
BIST
• In offline BIST, the circuit is
disconnected from its normal
operation and testing is carried out.
• It is applicable at manufacturing,
field, operational levels.
• It uses test pattern generators (TPG)
and output response analyzers
(ORA).
• It cannot detect errors at first
occurrence which is possible with
many online BIST techniques.
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 Types of Offline
BIST
• Functional offline BIST: The execution of
the test is based on the functional
description of circuit under test (CUT)
and employs a functional fault model.

• Structural offline BIST: The execution of

the test is based on the structure of
the CUT which uses explicitly structural
fault models.

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A Typical Logic BIST
System
Test Pattern Generator
(TPG)

Logic
Circuit Under Test
BIST
(CUT)
Controlle
r

Output Response Analyzer

(ORA)

Structural off-line BIST

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 Test Pattern
Generation
• Random Test pattern generation
○ Use pseudo random as input vectors
○ Typically use linear feedback shift registers
(LFSRs)

•TPG
○ Exhaustive testing
○ Pseudo-random testing
○ Pseudo-exhaustive testing

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Pseudo Random Test Generation

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 BIST Design
Rules
• Logic BIST requires much more stringent
design restrictions when compared to
conventional scan.
• when designing a logic BIST system, it is
essential that the circuit under test meet all
scan design rules and BIST specific design
rules, called BIST design rules

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Typical X-bounding
Methods

Methods for blocking an unknown (X) source

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 X-bounding
Methods
Depending on the nature of each unknown (X) source,
several X-bounding methods can be appropriate for
use.

Common problems:
(1) Increase the area of the design.
(2) Impact timing.

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 Typical Unknown
Sources
•Analog Blocks
▪ Adding bypass logic.
▪ Adding control-only scan point
•Memories and Non-Scan Storage
Elements
▪ Bypass logic
▪ Initialization
•Combinational Feedback Loops
▪ Scan points

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Typical Unknown Sources
(cont’d)
▪ Asynchronous Set/Reset Signals
▪ using the existing scan enable (SE) signal to
protect each shift operation and adding a
set/reset clock point (SRCK) on each set/reset
signal to test the set/reset circuitry.

SRCK
Set/Reset Circuitry
SE

Functional R
0 Q
Logic
1 D
Scan-In CK

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Typical Unknown Sources
(cont’d)

Asynchronous Set/Reset Signals

Shift Capture Shift

Capture Window Shift Window Window Window
Window C1
CK …
… … C2
SRCK

SE

Timing control diagram for testing data and set/reset faults

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Typical Unknown Sources
(cont’d)
Tri-State Buses
▪ Re-synthesize each bus with
multiplexers.
▪ One-hot decoder

A one-hot decoder for testing a tri-state bus with 2

drivers
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Typical Unknown Sources
(cont’d)
▪ False Paths
▪ 0-control point
▪ 1-control point
▪ Critical Paths
▪ Adding an extra input pin to a
selected combinational gate on
the critical path.

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Typical Unknown Sources
(cont’d)
▪ Multiple-Cycle Paths
▪ 0-control point
▪ 1-control point
▪ Holding certain scan cell output states
▪ Floating Ports
▪ PI or PO must have a proper connection to
Power (Vcc) or Ground (Vss).
▪ Floating inputs to any internal modules
must be avoided.

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Typical Unknown Sources
(cont’d)
▪ Bi-directional I/O Ports
▪Fix the direction of each bi-
directional I/O port to either input
or output mode.EN
SE D IO
Z
BIST_mode

Forcing a bi-directional port to output mode

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 LFSR
● Hardware circuit based on shift
register
○ With feedback
○ Good source of pseudo-random
pattern
● Used in many applications
○ For random number generation
○ Error checking (CRC)
○ Response compression

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 Standard
LFSR
• Consists of n D flip-flops and a selected
number of exclusive-OR (XOR) gates

h h h2 h1
n-1 n-2

S S S S
i0 i1 in-2 in-1

An n-stage (external-XOR) standard LFSR

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 Modular
LFSR
• Each XOR gate placed between two
adjacent D flip-flops

h1 h2 hn-2 hn-1

Si0 Si1 Sin-2 Sin-1

An n-stage (internal-XOR) modular LFSR

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 LFSR
Properties
• The internal structure of the n-stage LFSR
can be described by a
characteristic polynomial of degree n: f(x)

hi is either 1 or 0,depending on the feedback path

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 LFSR
•
Properties
Let Si represent the contents of the n-stage
LFSR after ith shifts of the initial contents,S ,of 0

the LFSR, and Si(x) be polynomial

representation of Si

If T is the smallest positive integer such that f(x) divides 1+ xT

the integer T is called the period of the LFSR.

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4-stage standard and modular
LFSRs

4-stage
standar
• 4-stage Modular
d and LFSR

modula f (x ) = 1 + x + x 4
r
LFSRs s
= x3 0

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 Hybrid
LFSR
a(x) = 1+ b(x)+ c(x)
Fully decomposable iff both b(x) and c(x) have no common terms
and there exists an integer j such that c(x ) =x j b (x ), j ≥1
Assume: f(x) is fully decomposable

f (x) = 1 + b(x)+ x jb(x)

A (hybrid) top-bottom LFSR [Wang 1988a] can be
constructed:
s (x )= 1+ ∧ xj+ xj b(x)
Indicate the XOR gate with one input
Is connected to the feedback path,
not between stages
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 5-stage hybrid
LFSRs

(a) 5-stage top-bottom

LFSR

(b) 5-stage bottom-top

LFSR

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 Exhaustive
Testing
• Exhaustive
Testing
▪ Applying n exhaustive patterns to an
2
n-input
combinational circuit under test
(CUT)
• Exhaustive pattern
generator
▪ Binary counter
▪ Complete LFSR

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 Binary
counter

X4
X1 X2 X3

Example binary counter as EPG

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 Complete
LFSR
0 0 0 1 0 0 1
0

(a) 4-stage standard (b) 4-stage modular

CFSR CFSR

0 0 0 1 1 0 0 0

(c) A minimized version of (d) A minimized version of

(a) (b)
Example complete LFSRs as EPG

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 Output Response
Analysis
•Ones count testing
•Transition count
testing
•Signature analysis

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 Ones Count
Assume theTesting
CUT has one output and the output
contains a stream of L bits. Let the fault-free output
response be
{r0 , r1 , r2 LrL−1}
Ones count testing will need a counter to count the number
of 1s in the bit
stream. POC (m) = (C(L, m) −1) /(2
L

−1) Signature
CUT
T Counter

CLK

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 Transition Count
•
Testing
Transition count testing is similar to that for ones
count testing, except the signature is defined as the
number of 1-to-0 and 0-to-1 transitions.

PTC (m) = (2C(L −1, m) −1) /(2 L

−1)
ri
r
i-1
T CUT D Counter Signature

CLK

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 Signature
Analysis
• Signature analysis is the most popular
compaction technique used today, based on
cyclic redundancy checking.

 Two signature analysis schemes

▪Serial signature analysis
▪Parallel signature analysis

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 Serial Signature
Analysis
• An n-stage single-input signature
register
h1 h2 h h
n-2 n-1

M r0 r1 r
rn-2 n-1

Define L-bit output

sequence M
M (x) = m0 + m1 x + m2 x +... + mL−1x
L−
1

Let the polynomial of the modular be f(x)

IF M (x) = q(x) f (x) + r(x) Signature is the

polynomial remainder,
r(x)

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 Exampl
e
M

A 4-stage
SISR 49
 Parallel Signature
Analysis
(MIS
R)
h1 h2 h h
n-2 n-1

r0 r1 r r
n-2 n-1

M M M
0
M1 2 Mn-2 n-1

An n-input MISR can be remodeled as a single-input SISR

with
effective input sequence M(x) and effective error polynomial E(x)

M (x) = M (x) + xM (x) +... + xn−2 M (x) + xn−1M (x)

0 1 n−2 n−1

E(x) = E (x) + xE (x) +...

+ xn−2 E (x) +
xn−1E (x)
0 1 n−2 n−1
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 4-stage
MISR
M0
1 0 0 10
M1
M2 0 1 0 10
M3 1 1 0 00
M0 M1 M2 M3
1 0 0 11
M 1 0 0 1 1 0 11

A 4-stage An equivalent M sequence

MISR
Aliasing probability

PPSA (n) = (2(mL−n) −1) /(2mL

−1)

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 Logic BIST
Architectures
•Four Types of BIST Architectures:
•No special structure to the CUT
•Make use of scan chains in the CUT
•Configure the scan chains for test pattern
generation and output response analysis
•Use concurrent checking circuitry of the design

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Self-Testing Using MISR and
Parallel SRSG
(STUMPS)
Contains a PRPG - pseudorandom pattern generator (SRSG -
Shift Register Sequence Generator) and a MISR - Multiple-input
signature register.
The scan chains are loaded in parallel from the PRPG.
The system clocks are then pulsed and the test
responses are scanned out to the MISR for compaction.
New test patterns are scanned in at the same time
when the test responses are being scanned out.
STUMPS - Self-Test Using MISR and Parallel Shift register sequence
generator
[Bardell
1982]

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 STUMPS
PRPG

PRPG
Linear Phase Shifter

CUT
CUT
(C or S)
(C or S)

Linear Phase Compactor

MISR
MISR

STUMPS A STUMPS-based
Architecture

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Built-In Logic Block Observer
(BILBO)
The architecture applies to circuits that can be
partitioned into independent modules (logic blocks).
Each module is assumed to have its own input and
output registers (storage elements), or such registers
are added to the circuit where necessary. The
registers are redesigned so that for test purposes
they act as PRPGs or MISRs.

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Built-In Logic Block
Observer

Y0 Y1 Y2
B2

B1
0
D D D
1
Q Q Q

Scan-In SCK X Scan-Out/X2

0
X1

A 3-stage
BILBO
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 Logic BIST
Architectures

B: board-level testing
C: combinational circuit
S: sequential circuit
TPG: Test Pattern Generator
ORA: Output Response Analyser

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