Unit-3

INPUT/OUTPUT
ORGANIZATION
Accessing I/O
Devices
 Accessing I/O devices

Processor Memory
Bus

I/O de vice1 I/O de vice n

•Multiple I/O devices may be connected to the processor and the memory via a
bus.
•Bus consists of three sets of lines to carry address, data and control signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the address lines.
•The device recognizes the address, and responds to the control signals.
•Processor requests for either Read / Write
•The data will be placed on Data lines
Accessing I/O devices (contd..)
 I/O devices and the memory may share the same address space:
 Memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer
data to or from an I/O device.
 eg. Move DATAIN, R0 and Move R0, DATAOUT
Accessing I/O devices (contd..)
 I/O devices and the memory may have different address spaces:
 Special instructions ( eg. IN and OUT) to transfer data to and from I/O
devices.
 I/O devices to use the special address space OR a part of the memory
address space
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory address
lines.
 In fact, address lines may be shared between I/O devices and memory,
with a control signal to indicate whether it is a memory address or an I/O
address.
•I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
•Data register holds the data being transferred to or from the processor.
•Status register holds the information necessary for the operation of the I/O
device.
•Data and status registers are connected to the data lines, and have unique
addresses.
•I/O interface circuit coordinates I/O transfers.
Accessing I/O devices (contd..)
 Recall that the rate of transfer to and from I/O devices is
slower than the speed of the processor. This creates the need
for mechanisms to synchronize data transfers between them.
 Program-controlled I/O:
 Processor repeatedly monitors a status flag to achieve the
necessary synchronization.
 Processor polls the I/O device.
 Two other mechanisms used for synchronizing data transfers
between the processor and memory:
 Interrupts.
 Direct Memory Access.
Registers used in the data transfer operation: Program
controlled I/O
An example
 Carriage return: is one of the control characters in
ASCII code, used to reset device’s to the beginning
of the line of text.
 Its ASCII value is 0x0D(13 in decimal).

 Line feed character moves cursor down to the next

line without returning to the beginning of the line.
 Its ASCII value is 0x0A(10 in decimal).
Interrupts
 Interrupts
 In program-controlled I/O, when the processor
continuously monitors the status of the device, it does
not perform any useful tasks.
 An alternate approach would be for the I/O device to
alert the processor when it becomes ready.
 Do so by sending a hardware signal called an interrupt to
the processor.
 At least one of the bus control lines, called an interrupt-
request line is dedicated for this purpose.
 Processor can perform other useful tasks while it is
waiting for the device to be ready.

 On the other hand, the processor must inform the

device that its request has been recognized so that it
may remove its interrupt-request signal. An
interrupt-acknowledge signal serves this function
 Interrupts (contd..)
COMPUTE routine Program 1 Interrupt Service routine
PRINT routine
1
2

Interrupt
occurs i
here
i +1

•Processor is executing the instruction located at address i when an interrupt occurs.

•When an interrupt occurs, control must be transferred to the interrupt service
routine.
•Routine executed in response to an interrupt request is called the interrupt-service
routine.
•Before transferring control, the current contents of the PC (i+1), must be saved in a
known location.
•This will enable the return-from-interrupt instruction to resume execution at i+1.
•Return address, or the contents of the PC are usually stored on the processor stack.
Interrupts (contd..)
 Treatment of an interrupt-service routine is very similar to that of a subroutine.
 However there are significant differences:
 A subroutine performs a task that is required by the calling program.
 Interrupt-service routine may not have anything in common with the program
it interrupts.
 Interrupt-service routine and the program that it interrupts may belong to
different users.
 As a result, before branching to the interrupt-service routine, not only the PC,
but other information such as condition code flags, and processor registers
used by both the interrupted program and the interrupt service routine must be
stored.
 This will enable the interrupted program to resume execution upon return from
interrupt service routine.
 A subroutine is called by a program instruction to perform a
function needed by the calling program. An interrupt-
service routine is initiated by an event such as an input
operation or a hardware error. The function it performs may
not be at all related to the program being executed at the
time of interruption.

 Before starting execution of ISR, any information

that may be altered during execution must be
saved. Later it must be restored when
interrupted program resumes.
Interrupts (contd..)
 Saving and restoring information can be done automatically by
the processor or explicitly by program instructions.

 Saving and restoring registers involves memory transfers:

 Increases the total execution time.
 Increases the delay between the time an interrupt request is
received, and the start of execution of the interrupt-service
routine. This delay is called interrupt latency.

 In order to reduce the interrupt latency, most processors save

only the minimal amount of information:
 This minimal amount of information includes Program
Counter and processor status registers.
 Any additional information that must be saved, must be
saved explicitly by the program instructions at the
beginning of the interrupt service routine.

 When these routines is used when external event takes

place in real time.
This application is referred to as REAL TIME
PROCESSING.
 A single interrupt request line may be used to serve n devices .

 All these lines connected to this line via switches to ground.

 If there is interrupt request, device closes switch.

 If all switches are open means interrupt request lines are

inactive, voltage then voltage at line is almost equal to Vdd.

 When device requests interrupt means switch is closed, voltage

on the line will drops to zero. Causing INTR received by the
processor is will be 1.

 If many devices request a interrupt then INTR is logical OR of

request from individual devices.

 Resistor R is called pull up resistor because It pulls line voltage

to high voltage state when switches are open.
Interrupt Nesting
 Interrupt should be disabled during execution of ISR to
ensure that a request from one device will not cause more
than one interruption.

 The same arrangement is required when more than one

device is involved, always continues to completion of one
ISR before processor accepts request from second device.

 Long delay in responding to int.request may lead to

erroneous operation.

 EX: Computer tracking time of day using real time clock.

Device sends intr rqst to processor at regular intervals.
 For each of these requests processor executes
short ISR to increment a set of counters in
memory that keep track of time in seconds,
minutes and so on.
 Interrupt
Sometimes it Nesting
may be necessary to accept an interrupt
request from a device during the execution of an interrupt-
service routine for another device. It suggests that I/O
devices should be organized in a priority structure. An
interrupt request from a high-priority device should be
accepted while the processor is servicing another request
from a lower-priority device.
The main advantage of the scheme is that it allows the processor to
accept interrupt requests from some devices but not from others,
depending upon their priorities.
Polling the status registers of the I/O devices is the simplest
mechanism.
 Controlling Device
Requests
 Some I/O devices may not be allowed to issue
interrupt requests to the processor.

 At device end, an interrupt-enable bit in a control

register determines whether the device is allowed to
generate an` interrupt request.

 At processor end, either an interrupt enable bit in the

PS register or a priority structure determines whether
a given interrupt request will be accepted.

37
 I/O device interface generates interrupt request
whenever it is ready for I/O transfer. EX: whenever
SIN flag is equal to 1.
 It is important to ensure that interrupt request are
generated only by those I/O devices that are
currently being used by given problem.
 We need some mechanism in the interface circuit
of individual devices to control whether a device is
allowed to generate an interrupt request.
 The control needed is provided in the form of
interrupt-enable bit in the device’s interface circuit.
 These are KEN,DEN flags in the register CONTROL.
 Whenever these flags are set to 1 then interface circuit
generates interrupt request.
 At the same time KIRQ and DIRQ are set to 1.
 If interrupt enable bit is 0 ,interface circuit will not generate
interrupt request.
 There are two independent mechanism for controlling
interrupt requests.
 1) At the device end, an interrupt-enable bit in a control
register determines whether the device is allowed to generate
interrupt request.
 2) At the processor end, an interrupt-enable bit in PS register
determines whether interrupt request is accepted or not.
 Consider a processor that uses vectored
scheme,where the starting address of interrupt-
service routine is stored at memory location
INTVEC.

 Interrupts are enabled by setting to 1, i.e an IE

bit.it is 9th bit in processor status word.
 Assume that at some point in main program if we
want to read character from keyboard and store
the characters in successive byte locations in the