Microprocessor & computer Architecture

Group Activity

Presented By- Group 2

8086 microprocessor

B.Tech Cse Cyber Security

 TEAM MEMBER
SR. NO. MEMBER NAME REG. NO TOPIC

1 PIYUSH KUMAR 231302160 INTRO AND PIN

2 VINIT SHEETAL 231302200 INTERRUPT

3 HARSH YADAV 231302171 INSTRUCTION SET

4 SAMARTH 231302204 REGISTER AND FLAGS

5 ANSHU 231302201 ADDRESSING MODE

6 AMAN 231302188 MEMORY MANAGEMENT

7 NITIN 231302191 MEMORY MANAGEMENT

8 DEEPINDER 231302173 PROGRAMMING

9 JASMIT 231302178 ARCHITECTURE

 CONTENT
● INTRODUCTION
● PIN DIAGRAM
● ARCHITECTURE
● INTERRUPT
● INSTRUCTION SET
● REGISTER AND FLAGS
● ADDRESSING MODE
● PROGRAMMING
● MEMORY MANAGEMENT
INTRODUCTION TO 8086 MICROPROCESSOR
The Intel 8086 is a 16-bit microprocessor introduced by Intel in 1978.

It was one of the first processors in the x86 family, forming the basis for modern computer architecture.

Features a 20-bit address bus, allowing access to up to 1 MB of memory.

Has a 16-bit data bus for efficient data transfer.

Operates at clock speeds ranging from 5 MHz to 10 MHz.

Utilizes a segmented memory model for efficient program management.

Supports:

● Multiprogramming

● Assembly-level programming
Piyush kumar
Pin Diagram
Pins
AD0–AD15 (Address/Data Bus) BHE’/S7 (Bus High Enable / Status):
● Multiplexed lines for lower-order address and ● BHE’ (active low) enables D8–D15 (upper data
data. bus).
● Useful for connecting 8-bit devices to upper byte.
● Act as A0–A15 during address phase (T1). ● Multiplexed with status line S7 (valid during T2–
T4).
● Act as D0–D15 during data phase (T2–T4). ● BHE’ is active (low) during T1.
A16–A19 (High-Order Address Bus):
RD’ (Read Control Signal):
● Carry high-order address bits.
● Active low output signal.
● Multiplexed with status signals:
● Indicates a read operation from memory or I/O.
○ A16/S3, A17/S4, A18/S5, A19/S6
Pins
READY:
NMI (Non-Maskable Interrupt):
● Acknowledgement signal from memory or ● Edge-triggered input.
slow I/O devices. ● Generates a Type 2 interrupt.
● Indicates completion of data transfer.
● Cannot be masked or disabled by
● Active High (1).
software.
● When low, the processor inserts wait states
until READY = 1.

INTR (Interrupt Request): INTA (Interrupt Acknowledge):

● Level-triggered interrupt input. ● Output signal to acknowledge interrupt.

● Sampled at the end of each instruction cycle. ● Active Low (0) during T2, T3, and Tw
● If active, the processor initiates interrupt of interrupt acknowledge cycle.
acknowledge cycle.
Pins
RQ’/GT1′ & RQ’/GT0′ (Request/Grant): TEST’:

● Used by local bus masters to request control ● Checked by a WAIT instruction.

of the local bus. ● If LOW (0), execution continues.
● Bi-directional pins. ● If HIGH (1), processor remains idle.
● RQ’/GT0′ has higher priority than
CLK (Clock Input):
RQ’/GT1′.
● The microprocessor releases the bus at the end ● Provides basic timing for processing and bus
of the current cycle. control.
● Asymmetric square wave, typically 33% duty
cycle.
LOCK’:
RESET:
● Signals that the bus must not be accessed by
other processors. ● Terminates current operation immediately.
● Remains active until the next instruction is
completed. ● Must be held HIGH (1) for at least 4 clock
● Used in multiprocessing environments. cycles.
Pins
M/IO’:
DEN (Data Enable):
● Distinguishes between Memory (M) and I/O (IO’)
● Enables transceivers (8286/8287).
operations.
● Active Low (0) during:
● M = High (1) → Memory access
○ Memory access
○ I/O access
● IO’ = Low (0) → I/O access
○ INTA cycles
DT/R (Data Transmit/Receive):
HOLD / HOLDA:
● Used with 8286/8287 transceivers.
● HOLD: Active High signal requesting the
bus.
● Controls data flow direction:
● When acknowledged, processor sends
HOLDA (High).
○ High = Transmit
● HOLDA issued during middle of T4 or T1
cycle.
Pins
ALE (Address Latch Enable):
● Active High pulse during T1 of any bus cycle.

● Used to latch address into 8282/8283 latches.

● ALE is never tri-stated (always valid signal).

Vcc:
● Power supply input: +5V DC.

GND:
● Ground reference.
 Architecture of 8086 Microprocessor
1. Bus Interface Unit (BIU) 2. Execution Unit (EU)

○ Fetches instructions from memory ○ Executes instructions decoded from the queue
○ Performs arithmetic and logical operations
○ Performs address calculation ○ Controls flags and registers
Handles communication with ○ Includes:
memory and I/O ■ ALU (Arithmetic Logic Unit)
○ Includes: ■ General Purpose Registers (AX, BX,
■ Segment Registers (CS, DS, CX, DX)
■ Control Flags and Condition Flags
SS, ES)
■ Instruction Pointer (IP)
■ Instruction Queue (6 bytes for
prefetching)

Jasmeet
Architecture of 8086 Microprocessor
 Interrupt
An interrupt is a mechanism that temporarily halts the normal execution of a program to handle an urgent event. Once the
interrupt is serviced, the microprocessor resumes execution from where it was interrupted.

How Interrupt Occurs ?

Interrupt
Triggering

Saving Processor
State

Identifying the
Interrupt Type

Jump to Interrupt
Service Routine

Execution of ISR

Resuming
VINIT SHEETAL Execution
Types of Interrupts
sdf
Here are diagrammatic chart : -

Hardware Interrupts Software Interrupts Exceptions

Maskable Non-Maskable Predefined

User-Defined
Interrupts Interrupts Software
Interrupts
(INTR) (NMI) Interrupts
Why Do We Need Interrupts?

1. Efficient CPU Utilization: Instead of continuously checking for input/output (polling), interrupts
allow the CPU to execute other tasks and respond only when required.
2. Multitasking: Allows execution of multiple tasks simultaneously, such as handling user input while
processing data.
3. Real-time Event Handling: Critical for real-time systems like industrial automation and embedded
devices.
4. Error Handling: Detects and responds to hardware failures and software errors.
5. I/O Operations: Enables faster communication with peripheral devices (disk drives, printers, etc.).
Interrupt Vector Table (IVT)

The Interrupt Vector Table (IVT) is a special

memory structure that stores the addresses
(segment: offset) of Interrupt Service
Routines (ISRs) for all possible interrupts in
an 8086-microprocessor system.
Let’s take example to understand

If an interrupt INT 10H (Video Services) occurs, the

microprocessor looks at:

● Interrupt Number = 10H (Decimal 16)

● IVT Entry Address = 10H × 4 = 40H
● The 4 bytes stored at memory location
0000:0040h contain the segment and offset of the
ISR.
Interrupt Control Logic Circuit

An external device triggers one of the interrupt lines

(TRAP, RST7.5, etc.).

The signal passes through masking logic and flip-

flops.

If enabled and unmasked:

● The interrupt request is recognized.

● CPU checks priority.

● If accepted, sends acknowledge signal (e.g.,

RST7.5 ack).

● Executes corresponding ISR (Interrupt

Service Routine).
HARSH YADAV
 Register in Microprocessor
What are Registers?

- Registers are high-speed, small-sized memory locations inside the

CPU.
- They temporarily hold data, addresses, or instructions during
processing.

Why are they important?

- Provide fast access for arithmetic/logical operations.

- Help manage program execution and data manipulation.

Types of Registers:

- General-purpose registers
- Special-purpose registers
- Segment registers
- Pointer and index registers

SAMARTH
1. General purpose register
•There are four 16 bit general purpose registers, i.e. AX, BX, CX, and
DX. These are used to store 16- bit data. They can also be used to
store 8 bit data and they are referred to AH, AL, BH, BL, CH, CL,
DH, and DL.
• AX register: It is also known as accumulator register. It is used to
store one of the operands for arithmetic operations.
• BX register: It is used as a base register. It is used to store the
starting base address of the memory area within the data segment.
• CX register: It is referred to as counter. It is used in loop instruction
to store the loop counter.
• DX register: This register is used to hold I/O port address for I/O
instruction.
2. Stack & base pointer register

SP - stack pointer
–It is 16-bit register.
–Always points to top item on the stack.
–Offset address relative to SS.
–An empty stack will had SP = FFFEh.

BP - base pointer
–It is 16-bit register.
–Primarily used to access parameters passed via the stack.
–Offset address relative to SS.
3. Source & Destination index register

•SI - source index register

–It is 16-bit register
–used for pointer addressing of data
–used as source in string processing instructions
–offset address relative to DS

• DI - destination index register

–It is 16-bit register
–used for pointer addressing of data
–used as destination in string processing instructions
–offset address relative to ES
4. Special Purpose Register:

- IP (Instruction Pointer): Holds the offset address of the next instruction to execute.
- FLAGS Register: Reflects the status of the processor (Zero, Carry, Sign, Overflow,
etc.)

Flags is a 16-bit register containing 9 one bit flags:

 FLAGS in 8086 Microprocessor
The 8086 microprocessor has a 16-bit FLAGS register that holds status flags and control flags. These
bits show the result of operations and control how the processor works.

Introduction to Flags

● Flags are flip-flops used to indicate the status of the processor.

● 8086 has a 16-bit flag register.
● It contains 9 active flags that affect/control operations.

Types of Flags

1. Status Flags – Reflect the result of an operation.

2. Control Flags – Control the operation of the CPU.

1. Status Flag :
Flag Description :

● CF (Carry Flag) :
Set when there is a carry/borrow in arithmetic ops.

● PF (Parity Flag):
Set if the result has even number of 1s.

● AF (Auxiliary Carry Flag):

Set if there’s a carry from bit 3 to 4 (BCD).

● ZF (Zero Flag):
Set if result of operation is zero.

● SF (Sign Flag):
Reflects the sign of result (MSB).

● OF (Overflow Flag)
Set if signed overflow occurs.
 2. Control Flag

1. Direction Flag (DF):

When it is set, string related instructions decrement index registers. When it is reset, string related
instructions increment index registers.

2. Interrupt-enable Flag (IF):

When it is set, enables maskable interrupts otherwise disable maskable interrupt.

3. Single-step Flag (TF):

- if set then single-step interrupt will occur after the next instruction.
Addressing Modes in Programming

•Addressing modes define how an instruction identifies

the location of its operands.
•They are essential for accessing data efficiently and
flexibly in assembly language and microprocessor
programming.

ANSHU
Immediate Addressing

•The operand is directly specified in the instruction.

• Fastest execution as no memory lookup is required.
• Commonly used for constant values.
Example: MOV A, #5 ; Load 5 directly into A.
Direct Addressing

• The address of the operand is directly mentioned in

the instruction.
• Simple and fast for accessing fixed memory
locations.
•Example: MOV A, 30h ; Load value from address
30h into A.
Indirect Addressing

• The address of the operand is stored in a register.

• Offers flexibility in accessing variable memory
locations.
• Common in accessing elements of an array.
•Example: MOV A, @R0 ; Load value from address
held in R0.
Register Addressing

• Operand is in a register specified in the instruction.

• Fastest form of addressing as it avoids memory
access.
•Example: MOV A, R1 ; Copy value of register R1 to
A.
Indexed Addressing

• Combines a base address with an offset stored in

an index register.
• Very useful in accessing array elements.
•Example: MOVC A, @A+DPTR ; Move code
byte from code memory pointed by A+DPTR to A.
Base-Indexed Addressing

• Uses a base register and an index register to determine the

operand address.
• Useful for complex data structures like structures and tables.
•Example:
MOV A, @DPTR+R0 ; Load value from address formed by
DPTR + R0.
Memory Management

•Memory management is the function responsible for managing the system's

memory hierarchy.
•It handles allocation and deallocation of memory blocks for programs and
processes.
•Key for system performance, stability, and multitasking.

AMAN
Types of Memory

•ROM (Read-Only Memory): Stores firmware and is non-volatile.

•RAM (Random Access Memory): Volatile memory for active data and
programs.
•Cache Memory: Very fast memory storing frequently accessed data to reduce
latency.
•Registers: Small, fast memory within the CPU holding operands and control
information.
Memory Addressing Modes
•Immediate: Operand is specified directly in the instruction.
•Direct: Address of the operand is specified explicitly.
•Indirect: Address of operand is held in a register or memory location.
•Indexed: Base address plus offset (index) for flexible data access.
•Used for efficient access and manipulation of memory in programs.
Segmentation in Microprocessors

•Memory is divided into logical segments: code, data, stack, extra.

•Each segment has a base address and an offset; total address = base +
offset.
•Common in x86 microprocessors (e.g., Intel 8086).
•Helps modularize programs and improve security and organization.
Paging in Microprocessors

•Memory is divided into fixed-size blocks called pages.

•Logical memory is divided into pages; physical memory is divided into frames.
•The page table maps pages to frames, enabling virtual memory.
•Paging supports larger programs and multitasking in modern OSes.
Assembly Language Basics
•Mnemonics used for instructions
•Operands: registers, memory, constants
•Directives: .model, .data, .code, etc.

DEPINDER KUMAR
Sample Program – Print Character
.model small
.stack 100h

.data
msg db 'A'

.code
main:
mov ax, @data ; initialize DS
mov ds, ax

mov ah, 02h ; DOS function: display character

mov dl, msg ; get the character from memory
int 21h

mov ah, 4Ch ; exit program

int 21h

end main
THANK YOU