Scribd
Upload
5 views

Apb Protocol (1)

The document discusses the design and implementation of the AMBA APB protocol, highlighting its evolution since its introduction by ARM in 1996 and its role in connecting low-power peripherals to high-performance buses. It includes a literature survey on various studies related to the protocol, operational states, and detailed descriptions of signal functions. The project successfully validated the protocol's functionality and reliability, with suggestions for future enhancements to improve performance and support advanced peripheral devices.

Uploaded by

skandanknight
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
5 views

Apb Protocol (1)

The document discusses the design and implementation of the AMBA APB protocol, highlighting its evolution since its introduction by ARM in 1996 and its role in connecting low-power peripherals to high-performance buses. It includes a literature survey on various studies related to the protocol, operational states, and detailed descriptions of signal functions. The project successfully validated the protocol's functionality and reliability, with suggestions for future enhancements to improve performance and support advanced peripheral devices.

Uploaded by

skandanknight
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 13

Design and Implementation of

AMBA APB Protocol


Introduction to AMBA APB Protocol
. Evolution of AMBA Protocol
● Introduced in 1996 by ARM, the AMBA protocol initially included APB and ASB, evolving to include AHB in
1999 (AMBA 2), AXI in 2003 (AMBA 3), and AXI4 and ACE in later versions for high-performance
interconnectivity.
● The protocol has advanced to support features like system-wide consistency (ACE) and high-speed transport
(CHI), addressing the growing complexity of SoC designs.
Introduction to AMBA APB Protocol

Bus Architecture of AMBA Protocol


● The AMBA bus architecture consists of three types: AHB/ASB for high performance, and APB for low power and low
bandwidth peripherals.
● The APB serves as a bridge for connecting peripheral devices like UART, timers, and keypads to high-performance buses
like AHB or ASB.
AMBA ARCHITECTURE
Literature Survey
Authors Paper Title Key Focus Findings Publication and Year

Shankar, Dipti Girdhar, Design and Verification of Design and verification of APB protocol enables low- International Journal of
Neeraj Kr. Shukla AMBA APB Protocol AMBA APB protocol. power, low-bandwidth Computer Applications
communication for Aspects
peripherals. June 2014.

Kommirisetti Bheema Raju, Design and Verification of APB protocol-compliant Efficient data communication Int. Journal of Engineering
Bala Krishna Konda, AMBA APB Protocol memory controller designed with minimal wait states, Research and Application
in VHDL and verified using suitable for low-bandwidth January 2017
ModelSim. peripherals in SoC designs.

S. Rai and V. P. Yadav Comparison between ARM Comparison of AMBA Successful verification of International Research
AMBA Protocols and protocols (APB, AHB, AXI) APB protocol with generated Journal of Engineering and
Verification of APB Protocol and verification of APB using waveforms using Aldec Technology (IRJET),
Using System Verilog & System Verilog & UVM. Riviera Pro simulator tool. June 2021
UVM

Mukunthan, K., APB Protocol Design and Design and implementation Demonstrated efficient IOP Conf. Series: Materials
Keerthivadana, K., Kiruthika, Verification using QuestaSim of APB protocol, focusing on read/write operations, verified Science and Engineering
K., Shruthi, K. various read/write cycles. using QuestaSim tool. 2021

K. Rawat, K. Sahni, and S. RTL Implementation for Design of APB bridge and Highlighted power International Conference on
Pandey AMBA ASB APB Protocol at ASB arbiter for efficient optimization and modular Signal Processing and
System on Chip Level master-slave communication design in VLSI systems, Integrated Networks (SPIN),
in SoCs. aligning with AMBA's 2015
reusable system philosophy.
Operation of APB

• IDLE: Default state with no operation.


• SETUP: Activates select signals for transmission.
• ACCESS: Data transfer with stable signals.
Write Operation (with and without wait)
Read Operation (with and without wait)
PIN Description
SIGNAL SOURCE Description WIDTH(Bi
t)
Transfer System Bus APB enable signal. If high APB is activated else APB is 1
disabled
PCLK Clock Source All APB functionality occurs at rising edge. 1
PRESET System Bus An active low signal. 1
n
PADDR APB bridge The APB address bus can be up to 32 bits. 8
PSEL1 APB bridge There is a PSEL for each slave. It’s an active high signal. 1
PENABL APB bridge It indicates the 2nd cycle of a data transfer. It’s an active high 1
E signal.
PWRITE APB bridge Indicates the data transfer direction. 1
PWRITE=1 indicates APB write access(Master to slave)
PWRITE=0 indicates APB read access(Slave to master)
PREADY Slave This is an input from Slave. It is used to enter access state. 1
Interface
PSLVER Slave This indicates a transfer failure by the slave. 1
R Interface
Write Operation

Without Wait

With Wait
Read Operation

Without Wait

With Wait
Conclusion

● The project successfully implemented the AMBA APB protocol using Verilog HDL, demonstrating
functional correctness through simulation results in the Xilinx environment.

● The data integrity was validated, ensuring that the data read from memory matched the data written,
confirming the protocol's reliability.

● The project highlights the importance of systematic design and verification processes, addressing the
increasing complexity of SoC designs.
Future Scope

● Future iterations of the APB protocol could enhance throughput and latency, optimizing performance for high-
speed applications while maintaining efficiency for low-power devices.

● The protocol can be extended to support advanced peripheral devices, such as new-generation sensors and
communication interfaces, enabling diverse and feature-rich embedded systems.

● Integration with emerging technologies like IoT and edge computing could enhance interoperability and
scalability, ensuring relevance in modern SoC architectures.

You might also like