CHAPTER 6:

ADVANCED
CONCEPTS
1
Computer
Architecture and
Organization
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LEARNING OBJECTIVES
 Discuss the principle behind instruction pipelining and how

it works in practice.

 Compare and contrast the various forms of pipeline

hazards.

 To introduce the concept of Parallel Processing.

 To introduce the concept of Operating System

 To introduce the concept of Cloud Computing and Quantum

Computing
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INSTRUCTION
PIPELINING
 Is similar to an assembly line in a manufacturing plant.
 products at various stages can be worked on simultaneously.
 new inputs are accepted at one end before previously
accepted inputs appear as outputs at the other end.
 Instruction pre-fetch / fetch overlap :- to fetch the next
instruction in parallel with the execution of the current
one.
 Pipelining requires registers to store data between
stages. (involves instructions buffering)
 This process will speed up instruction execution. (if equal
duration stages)

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CON…
In reality, doubling of execution rate is unlikely for two
reasons
 The execution time will generally be longer than the fetch
time.
 wait for some time before it can empty its buffer

 A conditional branch instruction makes the address of

the next instruction to be fetched unknown.
 wait until it receives the next instruction address from the
execute stage. Then wait until its fetched.
 Any Solutions?

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CON…
 To gain further speedup, the pipeline must have more
stages.
 Consider the following decomposition of the instruction
processing.
 Fetch instruction (FI)
 Decode instruction (DI)
 Calculate operands (CO)
 Fetch operands (FO)
 Execute instruction (EI)
 Write operand (WO)

 let us assume equal duration for each stages

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 This six- stage pipeline can reduce the execution time for
9 instructions from 54 time units to 14 time units.
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CONT…
Keep in mind that in the pervious diagram we assume that
 Each instruction goes through all six stages of the
pipeline.
 All of the stages can be performed in parallel.
 There are no memory conflicts. (FI, FO, and WO can occur
simultaneously)
 Another difficulty is the conditional branch instruction,
which can invalidate several instruction fetches.

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CONT..
 The greater the number of stages in the pipeline, the
faster the execution rate. But what is the burden
 Movement overhead
 There is some overhead involved in moving data from buffer
to buffer and in performing various preparation and delivery
functions.
 This can lengthen the total execution time of a single
instruction. This is significant when sequential instructions
are logically dependent
 Very complex:
 The amount of control logic required increases enormously
with the number of stages.

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PIPELINE HAZARDS
A pipeline hazard occurs when the pipeline, or some
portion of the pipeline, must stall because conditions do
not permit continued execution.
 Resource hazards/structural hazard:- occurs hardware
resource can’t support parallel execution of instructions.
 So instructions must be executed in serial
 Eg. main memory has a single read/write port, source
operand for instruction I1 is in memory

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CONT…
Data hazards: occurs when there is a conflict in the
access of an operand location.
 Two instructions in a program are to be executed in
sequence and both access a particular memory or
register operand.
ADD R1, R2 => R1 = R1 + R2

SUB R3, R1 => R3 = R3 - R1

ADD R1, R2

SUB R3, R1

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 I1 ADD R1, R2
SUB R3,
I2

DATA HAZARDS TYPES: RAW

R1
MOV R4,
I3
R1
I4 MUL R7,R8

There are three types of data hazards: RAW, WAR and WAW
 Read after write (RAW), or true dependency: An instruction
modifies a register or memory location and a succeeding
instruction reads the data in that memory or register location.
 A hazard occurs if the read takes place before the write operation is
complete.
 This is the most common type of hazard and the kind that we use
forwarding to overcome

Clock cycle
Clock cycle
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
I1 FI DI FO EI WO
I1 FI DI FO EI WO
I2 FI DI FO EI WO
I2 FI DI Idle FO EI WO
I3 FI DI FO EI WO
I3 FI DI Idle FO EI WO
I4 FI DI FO EI WO
I4 FI DI FO EI WO

without forwarding with forwarding

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DATA HAZARDS TYPES: WAR
 Write after read (WAR), or anti-dependency: An
instruction reads a register or memory location and a
succeeding instruction writes to the location.
 A hazard occurs if the write operation completes before the
read operation takes place.
 This can not happen in our example pipeline because
all reads are early (in FO) and all writes are late (in
WO).
 This hazard occurs when there are some instructions
that write results early in the instruction pipeline, and
other instructions that read a source late in the
pipeline.
 WAR hazards are rare

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DATA HAZARDS TYPES:
WAW
 Write after write (WAW), or output dependency:
Two instructions both write to the same location.
 A hazard occurs if the write operations take place in the
reverse order of the intended sequence.
 This data hazard only occurs if there are more than on write
stages in the pipeline.

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CONT…
Control hazards
 A control hazard, also known as a branch hazard
 Occurs when the pipeline makes the wrong decision on a
branch prediction
 therefore brings instructions into the pipeline that must
subsequently be discarded.

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 Memory
Instruction
Address

DEALING WITH
1 ADD R1, R2
2 BRZ 7
3 SUB R4, R1

BRANCHES
 Multiple streams
⁞

7
⁞
MOV R4,
10010

 A brute-force approach 8 MUL R3,R2

 Allow the pipeline to fetch both instructions, making use of

two streams
 Disadvantage:- contention delays for access to the registers
and to memory & additional branch instructions
 IBM 370/168 and the IBM 3033
Clock cycle Clock cycle

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9

I1 FI DI FO EI WO I1 FI DI FO EI WO

I2 FI DI FO EI WO I2 FI DI FO EI WO

I3 FI DI FO EI WO I3 FI DI FO EI WO

I4 FI DI FO EI WO I7 FI DI FO EI WO

I5 FI DI FO EI WO I8 FI DI FO EI WO

I6 FI DI FO EI WO

I7 FI DI FO EI WO Pipeline stream 2
I8 FI DI FO EI WO
(by assuming the branch is taken)

17
Pipeline stream 1 (by assuming the branch not taken)
DEALING WITH
BRANCHES
 Pre-fetch branch target

 The target of the branch is pre-fetched in addition to the

instruction following the branch

 then saved until the branch instruction is executed.

 If the branch is taken, the target has already been pre-

fetched.
 Used in IBM 360/91

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CONT…
 Loop buffer
 A loop buffer is a small, very-high-speed memory
 maintained by the instruction fetch stage of the pipeline and
 containing the n most recently fetched instructions, in sequence.
 If a branch is to be taken, the hardware first checks whether
the branch target is within the buffer.
 If so, the next instruction is fetched from the buffer.

 The loop buffer has three benefits:

 No memory reference required
 Useful for IF–THEN and IF–THEN–ELSE sequences
 This strategy is particularly well suited to dealing with loops, or
iterations
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CONT…
 Branch prediction:- Various techniques can be used to
predict whether a branch will be taken.
 Predict never taken
 Predict always taken
Static
 Predict by opcode
 Taken/not taken switch
 Branch history table Dynamic

Static: they do not depend on on the execution history

dynamic: They depend on the execution history

 Delayed branch: automatically rearranging instructions

within a program, so that branch instructions occur later
than actually desired.
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INTRODUCTION TO
PARALLEL PROCESSING,
 Some common methods used to enable parallel processing.

 Instruction-Level Parallelism (ILP)

 Executing multiple instructions simultaneously within a

single processor core.

 ILP aims to increase the efficiency of instruction

execution by overlapping different stages of instruction

processing.
 Techniques such as pipelining, superscalar execution

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CONT…
 Multiple-Processor Organizations

 A traditional way to increase system performance

 Uses multiple processors that can execute in parallel

to support a given workload.

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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
 SINGLE INSTRUCTION, SINGLE DATA (SISD) stream

 Traditional sequential computing model

 This architecture is the simplest form of processing and

represents the traditional von Neumann model of computing.

 Processor fetches instructions one at a time from memory

and executes them sequentially.

 Commonly found in traditional single-core processors used in

personal computers, laptops, and early computing systems.

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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
 SINGLE INSTRUCTION, MULTIPLE DATA (SIMD) stream

 Enables parallel execution of a single instruction on multiple

data elements simultaneously.

 The processor or core contains multiple processing units,

called lanes or vector units, which can execute the same

instruction on different data elements simultaneously.
 Common applications of SIMD include multimedia processing

(such as image and video processing), signal processing,

scientific simulations, and numerical computations.
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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
 MULTIPLE INSTRUCTION, SINGLE DATA (MISD) stream

 Involves multiple processors or cores executing different

instructions on the same stream of data simultaneously.

 Multiple processors or cores work in parallel, each executing

its own unique instruction on the same data.

 Often face challenges in terms of synchronization and

coordination between processors.

 MISD architectures have been explored in specialized

contexts such as fault-tolerant systems.

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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
 MULTIPLE INSTRUCTION, MULTIPLE DATA (MIMD) stream

 Multiple processors or cores execute different instructions on

different sets of data simultaneously.

 Each processor or core operates independently and can

execute its own instructions on its own data.

 Allows for a high degree of parallelism and enables the

execution of diverse tasks simultaneously.

 Commonly found in modern multi-core processors, distributed

systems, and parallel computing environments.

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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
MIMD architectures can be further classified into:
1. Shared Memory MIMD: multiple processors or cores have access

to a shared memory space.

 This allows them to communicate and share data easily. Synchronization

mechanisms are used to coordinate access to shared resources.

2. Distributed Memory MIMD: each processor or core has its own

local memory.
 Communication between processors occurs through message passing,

where data is explicitly transferred between processors. Distributed

memory systems are commonly used in cluster computing and
supercomputers.
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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
 MIMD architectures provide high flexibility and scalability, as

each processor or core can execute different instructions on

different sets of data.

 They are well-suited for parallelizing complex tasks, such as

scientific simulations, data analytics, and large-scale computations.

 Programming for MIMD architectures requires careful consideration

of load balancing, data distribution, and synchronization

mechanisms to efficiently utilize the available parallelism and
achieve high performance.

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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
Shared Memory MIMD architectures can be further classified into
SMP and NUMA

 Symmetric Multiprocessor (SMP) Systems: All processors have

equal access to the shared memory, allowing them to

communicate and share data efficiently.
 Characterized by a uniform memory access (UMA) architecture,

where accessing any memory location takes roughly the same

amount of time.
 SMP systems are widely used in multi-core processors, servers, and

high-performance computing.
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TYPES OF PARALLEL
PROCESSOR SYSTEMS
ARCHITECTURE
Shared Memory MIMD architectures can be further classified into

 Non-Uniform Memory Access (NUMA) Systems:

 Extension of SMP systems designed for scalability.

 Multiple processors or cores are connected to their own local memory

banks, and each processor has faster access to its local memory
compared to remote memory.
 This results in non-uniform memory access times.

 NUMA architectures are suitable for large-scale systems with a large

number of processors, where memory access needs to be efficiently

distributed across the system to avoid memory contention.

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INTRODUCTION TO
OPERATING SYSTEMS (OS)
 It is a system software that manages and controls the

hardware and software resources of a computer system.

 OS sits between the hardware and the application

software.

 The primary purpose of an OS is to provide an interface

between the user and the computer hardware, enabling

the user to run applications and utilize the system
resources efficiently.
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KEY FUNCTIONS AND
RESPONSIBILITIES OF AN
OPERATING SYSTEM
1. Process Management:
 The OS manages the execution of processes or tasks. It allocates

system resources, such as CPU time, memory, and input/output

devices, to different processes and ensures their proper execution.

2. Memory Management:
 The OS is responsible for managing the computer's memory. It

allocates and deallocates memory to processes, keeps track of

memory usage, and handles memory protection and virtual
memory mechanisms.

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KEY FUNCTIONS AND
RESPONSIBILITIES OF AN
OPERATING SYSTEM
3. File System Management:
 The OS provides a file system that organizes and manages files

stored on storage devices. It allows users to create, delete,

read, write, and organize files and directories.

4. Device Management:
 The OS manages the computer's input/output devices, such as

keyboards, mice, printers, disk drives, and network interfaces.

It handles device drivers, input/output requests, and provides
an interface for applications to interact with the devices.
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KEY FUNCTIONS AND
RESPONSIBILITIES OF AN
OPERATING SYSTEM
5. User Interface:
 The OS provides a user interface that allows users to interact

with the computer system. This can be in the form of a

command-line interface (CLI), graphical user interface (GUI),
or a combination of both.

6. Security:
 The OS ensures the security and protection of the system and

its resources. It provides mechanisms for user authentication,

access control, and data protection.
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KEY FUNCTIONS AND
RESPONSIBILITIES OF AN
OPERATING SYSTEM
7. Networking:
 Many operating systems include networking capabilities,

allowing computers to communicate and share resources over

a network. The OS manages network connections, protocols,
and configurations.

 Overall, an operating system plays a critical role in

managing the computer system's resources, providing a

user-friendly interface, and enabling the execution of
applications and services.
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READING ASSIGNMENT

What is Cloud Computing?

What is Quantum Computing?

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