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Ch#16 (CPU Structure and Function)

Chapter 16 discusses user-visible registers in CPUs, including General-Purpose Registers, Condition Code Registers, and Control and Status Registers, which help optimize memory usage and manage CPU operations. It also covers instruction pipelining, its performance limitations, pipeline hazards, and various strategies for handling branches to maintain efficiency. Techniques such as delayed branching and high-speed caches are highlighted as methods to mitigate delays caused by control hazards.

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30 views48 pages

Ch#16 (CPU Structure and Function)

Chapter 16 discusses user-visible registers in CPUs, including General-Purpose Registers, Condition Code Registers, and Control and Status Registers, which help optimize memory usage and manage CPU operations. It also covers instruction pipelining, its performance limitations, pipeline hazards, and various strategies for handling branches to maintain efficiency. Techniques such as delayed branching and high-speed caches are highlighted as methods to mitigate delays caused by control hazards.

Uploaded by

mairaawan52
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Chapter #16

User-visible registers: Enable the machine- or


assembly language programmer to minimize main
memory references by optimizing use of registers.
A General-Purpose Register (GPR) is a type of register in a CPU that is
used to store data temporarily during program execution. These
registers can hold operands, intermediate results, memory
addresses, and other values needed for computations.
A Condition Code Register (CCR) (also known as Flags Register or
Status Register) is a special-purpose register in the CPU that holds
flags representing the outcomes of arithmetic and logical
operations. These flags influence decision-making in programs by
enabling conditional execution (e.g., jumping, branching).
Control and Status Registers (CSRs) are special-purpose
registers used by the CPU to manage its operation,
execution mode, and status reporting. These registers
control privileged operations, handle interrupts, and
maintain the overall state of the processor.
The Instruction Cycle is the process a CPU follows to execute an
instruction. When Indirect Addressing is used, an extra step is
required to fetch the actual operand from memory.
Instruction Pipelining is a technique used in CPUs to overlap the
execution of multiple instructions by breaking them into different
stages. This increases the throughput of the processor, allowing it to
execute multiple instructions at the same time.
Performance Limitations in Instruction Pipelining
Several factors limit the performance enhancement of instruction
pipelining:
1.Unequal Stage Durations → If the six pipeline stages do not take
equal time, some stages may have to wait, reducing efficiency.
2.Interrupts → Unexpected events like interrupts can also disrupt the
pipeline, requiring a reset and reloading of instructions.
3.Pipeline Clearing → When a branch is taken (as shown in Figure
16.11), the pipeline must discard incorrect instructions, causing a
delay (stall) before the correct instruction (e.g., instruction 15) enters
the pipeline.
4.Performance Penalty → Due to pipeline stalls from branches and
interrupts, some cycles may complete without executing useful
instructions, reducing the expected speedup.
Pipeline hazards are situations that cause delays in instruction
execution by preventing the smooth flow of instructions through the
pipeline. These hazards reduce the efficiency of pipelining and lead
to pipeline stalls (bubbles).
A pipelining stall, happens when the next instruction cannot
execute in the following clock cycle. This causes a delay in the
Data Dependencies
• Read After Write (RAW) – True Dependency
Occurs when an instruction needs to read a value that is yet to be
written by a previous instruction.
Example:
Instruction 1: R1 = R2 + R3
Instruction 2: R4 = R1 + R5 ; RAW hazard – needs the updated
value of R1
2. Write After Read (WAR) – Anti Dependency
Occurs when an instruction writes to a destination before it has
been read by a previous instruction.
Example:
Instruction 1: R4 = R1 + R2
Instruction 2: R1 = R3 + R5 ; WAR hazard – writes R1 before
Instruction 1 reads it
Data Dependencies
3. Write After Write (WAW) – Output
Dependency
Happens when two instructions write to the
same register, and the second write happens
before the first.
Example:
Instruction 1: R1 = R2 + R3
Instruction 2: R1 = R4 + R5 ; WAW hazard –
overwrites R1 before Instruction 1 writes it
A control hazard occurs when the
processor does not know the
outcome of a branch instruction
(e.g., whether to go to the next
instruction or jump somewhere else)
and thus doesn't know which
instruction to fetch next.
Dealing with branches
A variety of approaches have been taken for dealing
with conditional branches:
• Multiple streams
• Prefetch branch target
• Loop buffer
• Branch prediction
• Delayed branch
A high-speed cache (buffer) stores recently executed
branch instructions,
especially useful for small loops.
•If a loop is detected, the processor fetches instructions from
the buffer instead of memory.
Delayed branching is a technique used in pipelining where the
instruction right after a branch is always executed, no matter if the
branch is taken or not. This helps keep the pipeline running
smoothly and reduces delays.

Delayed branching is a technique used to minimize the performance


penalty caused by control hazards (i.e., branch instructions like if,
for, while, etc.) that disrupt the smooth flow of the instruction
pipeline.

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