PRAVIN ROHIDAS PATIL COLLEGE OF DEGREE ENGG.

& TECHNOLOGY

MEMORY AND PERIPHERALS

INTERFACING

CHAPTER 3 – THE INTEL MICROPROCESSORS 8086 ARCHITECTURE

SUBJECT – MICROPROCESSOR (CSC405)
SEMESTER – FOURTH
BY– MRS PRACHI KALPANDE

1
INTERFACING
 Memories and I/O Interfacing

⮚ Memory is an important element of micro-

computer, it is used for storing the data,
programs and result.
 INTERFACING
⮚ Interface is the path for communication between two components.
Interfacing is of two types, memory interfacing and I/O interfacing.
❖ Memory Interfacing
⮚ When we are executing any instruction, we need the
microprocessor to access the memory for reading instruction codes and
the data stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to registers.
▶ The interfacing process includes some key factors to match with the
memory requirements and microprocessor signals. The interfacing circuit
therefore should be designed in such a way that it matches the memory
signal requirements with the signals of the microprocessor.
❖ IO Interfacing
▶ There are various communication devices like the keyboard, mouse,
printer, etc. So, we need to interface the keyboard and other devices with
the microprocessor by using latches and buffers. This type of interfacing is
known as I/O interfacing.
Block Diagram of Memory and I/O
Interfacing
 ADDRESS DECODING
▶ Address decoding refers to the way a computer
system decodes the addresses on the address bus
to select memory locations in one or more memory or
peripheral devices.
 ABSOLUTE DECODING
⮚ In the absolute decoding technique the memory chip is selected only for
the specified logic level on the address lines: no other logic levels can
Address Decoding Techniques
select the chip.
⮚ Below figure the memory interface with absolute decoding.
⮚ Two 8K EPROMs (2764) are used to provide even and odd memory banks.
⮚ Control signals BHE and Ao are use to enable output of odd and even
memory banks respectively.
⮚ As each memory chip has 8K memory locations, thirteen address lines
are required to address each locations, independently.
⮚ All remaining address lines are used to generate an unique chip select
signal. This address technique is normally used in large memory
systems.
 LINEAR DECODING
▶ In small system hardware for the decoding logic can
be eliminated by using only required number of
addressing lines (not all). Other lines are simple
ignored. This technique is referred as linear decoding
or partial decoding.
⮚ Control signals BHE and Ao are used to enable odd
and even memory banks, respectively. Figure shows
the addressing of 16K RAM (6264) with linear
decoding.
 MEMORY MAPPED IO
▶ It considers them like any other memory
location.
▶ They are assigned a 16-bit address within the
address range of the 8085.
▶ The exchange of data with these devices
follows the transfer of data with memory.
The user uses the same instructions used for
memory.
 IO Mapped IO
⮚It treats them separately from memory.
⮚ I/O devices are assigned a “port number” within
the 8-bit address range of 00H to FFH.
⮚ The user in this case would access these devices
using the IN and OUT instructions only.
 IO mapped IO V/s Memory
Mapped IO
Memory Mapped IO IO Mapped IO
⮚ IO is treated as memory. ⮚ IO is treated IO. 8- bit
16-bit addressing. addressing.
⮚ More Decoder Hardware. ⮚ Less Decoder Hardware.
⮚ Can address 216=64k ⮚ Can address 28=256
locations. locations.
⮚ Less memory is available. ⮚ Whole memory address
space is available.
 BASIC DESCRIPTION OF THE 8255
• It is an I/O port chip used for interfacing I/O
devices with microprocessor system.
• It is device used to implement parallel data
transfer between processor and slow
peripheral devices like ADC, DAC, keyboard,
7-segment display, lCD etc.
 BASIC DESCRIPTION OF THE 8255
• It consists of 40 pins and operates in +5V regulated power supply.
• Port C is further divided into two 4-bit ports i.e. port C lower and port C
upper.
• port C can work in either BSR (bit set rest) mode or in mode 0 of input-
output mode of 8255.
• Port B can work in either mode 0 or in mode 1 of input-output mode.
• Port A can work either in mode 0, mode 1 or mode 2 of input-output
mode.
• It has two control groups, control group A and control group B.
• Control group A consist of port A and port C upper.
• Control group B consists of port C lower and port B.
• Depending upon the value if CS’, A1 and A0 we can select different ports
in different modes as input-output function or BSR.
• This is done by writing a suitable word in control register (control word
D0-D7).
Depending upon the value if CS’, A1 and A0 we can select different ports in different
modes as input-output function or BSR. This is done by writing a suitable word in
control register (control word D0-D7).

CS’ A1 A0 Selection Address

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

Control
0 1 1 83 H
Register

1 X X No Seletion X
 BASIC DESCRIPTION OF THE 8255
Features:
⮚ It is a programmable device.

⮚ It has 24 I/O programmable pins like PA,PB,PC (3-8

pins).

⮚ T T L compatible.
 BASIC DESCRIPTION OF THE 8255
⮚ 8255A has three ports
⮚ PORT A
⮚ PORT B
⮚ PORT C
⮚ Port A and Port B are 8 bit parallel ports.
⮚ Port C can be split into two parts, i.e. PORT C
lower (PC0-PC3) and PORT C upper (PC7-PC4)
by the control word.
 8255
⮚ These three ports are further divided into two
groups,
⮚ i.e. Group A includes PORT A and upper PORT C.
⮚ Group B includes PORT B and lower PORT C
⮚ These two groups can be programmed in
three different modes.
 OPERATING MODES OF 8255
• Three operating modes :
– Mode-0(simple I/O port)
– Mode-1(Handshake I/O port)
– Mode-2(Bidirectional I/O port)
 MODE 0
⮚ In this mode, Port A and B is used as two
8-bit ports and Port C as two 4-bit ports.
⮚ Each port can be programmed in either
input mode or output mode where
outputs are latched and inputs are not
latched.
⮚ Ports do not have interrupt capability.
⮚ Ports in mode 0 is used to interfaces LEDs,
Hexa keypad and 7 segment LEDS to the
processor.
 MODE 1
⮚ In this mode, Port A and B is used as 8-bit I/O
ports.
⮚ They can be configured as either input or
output ports.
⮚ Each port uses three lines from port C as
handshake signals.
⮚ Inputs and outputs are latched
• MODE 1 :(Input/output with Hand shake)
• In this mode, input or output is transferred by
hand shaking Signals.

Compute DATA BUS Printer

r STB
ACK

Busy

• Handshaking signals is used to transfer data

between whose data transfer is not same.
⮚ Example:
⮚ The computer send the data to the printer large
speed compared to the printer.
⮚ When computer send the data according to the
printer speed at the time only, printer can accept.
⮚ If printer is not ready to accept the data then after
sending the data, computer uses another
handshaking signal to tell printer that valid data is
available on the data bus.
⮚ Each port uses three lines from port C as
handshake signals
 MODE 2
⮚ In this mode, Port A can be configured as
the bidirectional port and Port B either in
Mode 0 or Mode 1.
⮚ Port A uses five signals from Port C as
handshake signals for data transfer.
⮚ The remaining three signals from Port C can
be used either as simple I/O or as
handshake for port B.
MODE 2:bi-directional I/O data transfer:
• This mode allows bidirectional data transfer over
a single 8-bit data bus using handshake signals.
• This feature is possible only Group A
• Port A is working as 8-bit bidirectional.
• PC3-PC7 is used for handshaking purpose.
• The data is sent by CPU through this port , when
the peripheral request it.
• CONTROL WORD FORMATS:
• In the INPUT mode , When RESET is High all 24
pins (3-ports) be a input mode.
• i.e all flip flops are cleared and the interrupts are
rest.
• This condition is maintained even after RESET
goes low.
• This can be avoid by writing single control word to
the control registers , when required.
Pin Diagram
 FUNCTION OF PINS:
⮚ Data bus(D0-D7):These are 8-bit bi-directional buses,
connected to 8086 data bus for transferring data.

⮚ CS: This is Active Low signal. It stands for Chip Select. A

LOW on this input selects the chip and enables the
communication between the 8255 and the CPU.

⮚ Read: This is Active Low signal, when it is Low the

microprocessor reads data from a selected I/O port of
8255A.

⮚ Write: This is Active Low signal, when it is Low the

microprocessor writes data into a selected I/O port .
• Address (A0-A1):This is used to select the ports.

A1 A0 Select

0 0 PA

0 1 PB

1 0 PC

Control
1 1
reg.
⮚ RESET: This is used to reset the device. That means
clear control registers.

⮚ PA0-PA7:It is the 8-bit bi-directional I/O pins used to

send the data to peripheral or to receive the data from
peripheral.

⮚ PB0-PB7:Similar to PA

⮚ PC0-PC7:This is also 8-bit bidirectional I/O pins. These

lines are divided into two groups.
⮚ PC0 to PC3(Lower Groups)
⮚ PC4 to PC7 (Higher groups)
⮚ These two groups working in separately using 4
data’s.
BLOCK DIAGRAM-8255
⮚ Data Bus buffer:
⮚ It is a 8-bit bidirectional Data bus.

⮚ Used to interface between 8255 data bus with

system bus.

⮚ The internal data bus and Outer pins D0-D7 pins

are connected in internally.

⮚ The direction of data buffer is decided by

Read/Control Logic.
Read/Write Control Logic:
• This is getting the input signals from control
bus and Address bus

• Control signal are RD and WR.

• Address signals are A0,A1,and CS.

• 8255 operation is enabled or disabled by CS.

GROUP A AND GROUP B CONTROL:
• Group A and B get the Control Signal from CPU and
send the command to the individual control blocks.
• Group A send the control signal to port A and Port C
(Upper) PC7-PC4.
• Group B send the control signal to port B and Port C
(Lower) PC3-PC0.
• PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.
PORT C:
• This is a 8-bit Unlatched buffer Input and an
Output latch.
• It is splitted into two parts.
• It can be programmed by bit set/reset operation.
 OPERATION MODES IN 8255
• Two operating modes:
– I/O mode( mode 0, mode 1, mode2)
– Bit set/Reset mode
 OPERATION MODES:
BIT SET/RESET MODE:
• The PORT C can be Set or Reset by sending OUT
instruction to the CONTROL registers.
• If MSB of control word (D7) is 0, PPI works in BSR
mode. In this mode only port C bits are used for
set or reset.
 OPERATION MODES:
I/O MODES:
• MODE 0(Simple input / Output):
• In this mode , port A, port B and port C is used as
individually (Simply).
• Features:
• Outputs are latched , Inputs are buffered not latched.
• Ports do not have Handshake or interrupt capability.
 CONTROL WORDS
• Two control words:
– I/O mode set control word(MSW)
– Bit set/reset control word(BSR)
• MSW is used to specify I/O functions.
• BSR is used to set/reset individual pins of Port C.
• Both the control words are written in the same
control register.
 CONTROL WORDS
• 8255 ports are programmed by writing
control word in the control word in the
control register.
• For setting I/O functions and mode of
operation the I/O mode set control word is
send to control register.
• For setting/ resetting pins of port C, the bit
set/reset control word is send to control
register.
 FOR BIT SET/RESET MODE:
• This is bit set/reset control word format.
D7 D6 D5 D4 D3 D2 D1 D0

X X X BIT
SET/RESET
Don’t care 1=SET
0=RESET

Bit select
0 1 2 3 4 5 6 7
B0
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
B1 0 0 1 1 1 1
0 0

B2SET/RESET FLAG
BIT
=0 Active
 CONTROL WORDS
• FOR BIT SET/RESET MODE:

• PC0-PC7 is set or reset as per the status of D0.

• A BSR word is written for each bit
• Example:
– PC3 is Set then control register will be 0XXX0111.
– PC4 is Reset then control register will be 0XXX0100.
• X is a don’t care.
 FORMAT OF I/O MODE:
The mode format for I/O as shown in figure
D D D D D D D D
7 6 5 4 3 2 1 0

Group A Group B
Port C Upper
1=Input Port C Lower
Mode set
0=Output 1=Input
1-I/O mode
0-BSR mode Port B 0=Output
1=Input Port B
0=Output 1=Input
Mode 0=Output
selection
Mode selection
00=mode 0
0=mode 0
01=mode 1
1=mode 1
1x=mode 2
• The control word for both mode is same.
• Bit D7 is used for specifying whether word
loaded in to Bit set/reset mode or Mode
definition word.
• D7=1=Mode definition mode.
• D7=0=Bit set/Reset mode.
 BASIC DESCRIPTION OF THE 8255
⚫The 8255 provides 24 I/O lines which may
be individually programmed in 2 groups of
12 I/O lines and used in 3 major modes of
operation.
⚫These 24 I/O lines organized as three 8-bit
I/O ports labeled A, B, and C.
⚫The chip interfaces directly to the data bus
of the processor, allowing its function to be
programmed;
⚫That is, in one application a port may appear
as an output, but in another, by
reprogramming it, as an input.
 BASIC DESCRIPTION OF THE 8255
⚫Each of the ports, A or B, can be
programmed as an 8-bit input or output
port.
⚫Port C can be divided in half, with the topmost
or bottommost four bits programmed as inputs
or outputs.
⚫Individual bits of a particular port cannot be
programmed.
 PIN CONFIGURATION OF THE 8255
⚫ The pin configuration of the 8255 is shown in Figure 1.
▪ GND: System ground
▪ VCC: System power
▪ RESET: A high on this input clears the control register and all ports are set to
the input mode.
▪ PA7-0: Port A bits
▪ PB7-0: Port B bits
▪ PC7-0: Port C bits
▪ D7-0: A bi-directional, tri-state data bus lines, connected to the system data
bus.
▪ RD’: A read input control, that is low during CPU read operations.
▪ WR’: A write input control, that is low during CPU write operations.
▪ CS’: A chip select control. A low on this input enables the 8255 to respond
to RD’ and WR’ signals. RD’ and WR’ are ignored otherwise.
▪ A1-0: Address lines which in conjunction with RD’ and WR’, control the
PIN CONFIGURATION OF THE 8255

Figure 1: Pin configuration of the

8255
Table 1: Selection of 8255 ports using
address lines.
 BLOCK DIAGRAM OF THE 8255
⚫The block diagram of the 8255 is shown in Figure 2.
⚫Data Bus Buffer:
◦ This 3-state bidirectional 8-bit buffer is used to
interface the 8255 to the system data bus.
◦ Data is transmitted or received by the buffer upon
execution of input or output instructions by the CPU.
◦ Control words and status information are also transferred
through the data bus buffer.
⚫Read/Write and Control Logic:
◦ The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words.
◦ It accepts inputs from the CPU Address and Control
busses and in turn, issues commands to both of the
Control Groups.
 BLOCK DIAGRAM OF THE 8255
▪ Group A and Group B Controls:
▪ The functional configuration of each port is programmed by the
systems software.
▪ The CPU outputs a control word to the 8255.
▪ The control word contains information such as mode, bit set, bit
reset, etc., that initializes the functional configuration of the
82C55A.
▪ Each of the Control blocks (Group A and Group B) accepts
commands from the read/write control logic, receives control
words from the internal data bus and issues the proper
commands to its associated ports.
▪ Control Group A - Port A and Port C upper (C7-C4)
▪ Control Group B - Port B and Port C lower (C3-C0)
▪ The control word register can be both written and read as
shown in Table 1.
 BLOCK DIAGRAM OF THE 8255
▪ Ports A, B, and C:
▪ The 8255 contains three 8-bit ports (A, B, and C).
▪ All can be configured in a wide variety of
functional characteristics by the system software.
FIGURE 2: BLOCK DIAGRAM OF THE 8255
 INTERFACING THE 8255 TO THE 8086 PROCESSOR
⚫Example 1: Show how to interface an 8255 chip to
the low byte of the 8086 (D0-D7). Assume the
following I/O address ports are used.
Step (1): Design the address decoding
Port Port
A11-A8 A7-A4 A3 A2 A1 A0
A -A Name Address
15 12
Port A 00H
0000 0000 0000 0 0 0 0 Port B 02H
0000 0000 0000 0 0 1 0 Port C 04H
0000 0000 0000 0 1 0 0
Control 06H
0000 0000 0000 0 1 1 0

Port Enable
Chip Select (CS’)
Select Even Byte
(A1 A0)
(D0-D7)
Step(2): Design control logic (IOW’ & IOR’)
Figure 3: Interface of the 8255 in Example 1
 PROGRAMMING THE 8255
⚫There are three basic modes of
operation that can be selected by the
system software:
◦ Mode 0: Basic input/output
◦ Mode 1: Strobed Input/output
◦ Mode 2: Bi-directional Bus
 PROGRAMMING THE 8255
⚫When the reset input of the 8255 goes
"high" all ports will be set to the input
mode with all 24 port lines held at a
logic "one" level.
⚫After the reset is removed the 8255 can
remain in the input mode with no
additional initialization required.
⚫During the execution of the system
program, any of the other modes may be
selected by using a single output
instruction.
⚫The modes for Port A and Port B can be
separately defined, while Port C is
divided into two portions.
 PROGRAMMING THE 8255
⮚ Figure 4 shows the format of the control
byte used to program the 8255.
⮚ There are two types of control bytes:
⮚ (a) When bit 7 = 0, a bit set/reset operation
is indicated;
⮚ (b) When bit 7 = 1, any of the modes 0, 1, or
2 can be programmed.
⮚ The ports in Group A can be programmed
for any of modes 0, 1, or 2.
⮚ The ports in Group B can only be
programmed for modes 0 or 1.
Figure 4: The format of the control byte of the 8255.
 PROGRAMMING THE 8255
⮚ Example 2: Write the 80x86
initialization routine required to
program the 8255 in Figure 5 for mode
0, with port A as an output and ports B
and C inputs
⮚ The control word is formed as:
⮚ 🞄 1 00 0 1 0 1 1 = 8BH
⮚ The program is as follows:
⮚ 🞄 MOV AL,8BH ;Control byte to AL
⮚ 🞄 OUT 6,AL ;Write to control port
Figure 5: Circuit design of Example 2.
 PROGRAMMING THE 8255
⚫Example 3: Write an 80x86 program to
input a byte from port B of the PPI chip
in pervious example and output this
byte to port A of the same chip. Assume
the chip has been programmed as in
the previous example.

◦ The program requires two instructions.

IN AL, 2 ; Get data from port B

OUT 0,AL; Output the data to port A

 OPERATING MODES OF THE 8255
⮚ The 8255A can be programmed in three modes (0, 1,
2) as shown in Figure 6:
⮚ Mode 0 (Basic I/O): three simple I/O ports.
⮚ Ports A and B operate as either inputs or outputs.
⮚ Port C is divided into two 4-bit groups either of which can be
operated as inputs or outputs.
⮚ Mode 1 (Strobed I/O): two hand shaking I/O
ports.
⮚ Ports A and B operate as either inputs or outputs as in
mode 0
⮚ Port C is used for handshaking and control.
⮚ Mode 2 (Strobed Bidirectional I/O): a
bidirectional I/O
⮚ port with five hand shaking signals.
⮚ Port A is bidirectional (both input and output).
⮚ Port C is used for handshaking.
⮚ Port B is not used.
⮚
Figure 6: The three basic modes of the 8255.
 OPERATING MODES OF THE 8255
⮚ Mode 0 (Basic Input / Output)
⮚ This mode provides simple input and
output operations for each of the three
ports.
⮚ No handshaking is required, data is
simply written to or read from a specific
port.
⮚ The basic features of this mode are:
⮚ Two 8-bit ports and two 4-bit ports
⮚ Any Port can be input or output
⮚ Outputs are latched
⮚ Input are not latched
⮚ 16 different input / output configurations
Table 2: Mode 0 port definition.
 OPERATING MODES OF THE 8255
⮚ Mode 1 (Strobed Input / Output)
⮚ This mode provides a means for transferring I/O
data to or from a specified port in conjunction
with strobes or “hand shaking” signals.
⮚ In this mode, port A and port B use the lines on
port C to generate or accept these “hand
shaking” signals.
⮚ The basic features of this mode are:
⮚ Two Groups (Group A and Group B).
⮚ Each group contains one 8-bit port and one 4-
bit control/data port.
⮚ The 8-bit data port can be either input or output.
⮚ Both inputs and outputs are latched.
⮚ The 4-bit port is used for control and status of the 8-
bit port.
 OPERATING MODES OF THE 8255
⮚ Mode 1 (Strobed Input / Output)
⮚ Figure 7 shows the control signals for input configuration.
⮚ STB (Strobe Input)
⮚ A “low” on this input loads data into the input latch.
⮚ IBF (Input Buffer Full F/F)
⮚ A “high” on this output indicates that the data has been loaded into
⮚ the input latch.
⮚ IBF is set by STB’ input being low and is reset by the rising edge of the RD’
input.
⮚ INTR (Interrupt Request)
⮚ A “high” on this output can be used to interrupt the CPU when and input
device is requesting service.
⮚ INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is a
“one”.
⮚ It is reset by the falling edge of RD.
⮚ This procedure allows an input device to request service from the
⮚ CPU by simply strobing its data into the port.
⮚ INTE A: Controlled by bit set/reset of PC4.
⮚ INTE B: Controlled by bit set/reset of PC2.
Figure 7: Mode 1 input.
 OPERATING MODES OF THE 8255
⮚ Mode 1 (Strobed Input / Output)
⮚ Figure 8 shows the control signals for output
configuration.
⮚ OBF - Output Buffer Full F/F:
⮚ The OBF’ output will go “low” to indicate that the
CPU has written data out to be specified port.
⮚ The OBF’ F/F will be set by the rising edge of the
WR input and reset by ACK input being low.
⮚ ACK - Acknowledge Input):
⮚ A “low” on this input informs the 82C55A that the
data from Port A or Port B is ready to be accepted.
⮚ A response from the peripheral device indicating
that it is ready to accept data
 OPERATING MODES OF THE 8255
⮚ Mode 1 (Strobed Input / Output)
⮚ INTR - (Interrupt Request):
⮚ A “high” on this output can be used to interrupt
the CPU when an output device has accepted data
transmitted by the CPU.
⮚ INTR is set when ACK is a “one”, OBF is a “one” and
INTE is a “one”.
⮚ It is reset by the falling edge of WR.
⮚ INTE A: Controlled by bit set/reset of PC6.
⮚ INTE B: Controlled by bit set/reset of PC2.
Figure 8: Mode 1 output.
 OPERATING MODES OF THE 8255
⮚ Mode 2 (Strobed Bidirectional Input / Output)
⮚ This mode provides a means for
communicating with a peripheral device or
structure on a single 8-bit bus for both
transmitting and receiving data (bidirectional
bus I/O).
⮚ In this mode, port A uses the lines on port C
to generate or accept these “hand shaking”
signals.
⮚ The basic features of this mode are:
⮚ Used in Group A only.
⮚ One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C)
⮚ Both inputs and outputs are latched.
 OPERATING MODES OF THE 8255
⮚ Mode 2 (Strobed Bidirectional Input / Output)
⮚ Figure 9 shows the control signals for mode 2
configurations.
⮚ Input Operations:
⮚ STB’ - (Strobe Input): A “low” on this input
loads data into the input latch.
⮚ IBF - (Input Buffer Full F/F): A “high” on this
output indicates that data has been loaded into
the input latch.
⮚ INTE 2 - (The INTE flip-flop associated with IBF):
Controlled by bit set/reset of PC4.
⮚ INTR - (Interrupt Request): A high on this
output can be used to interrupt the CPU for
both input or output operations.
Figure 9: Mode 2 control signals.
 OPERATING MODES OF THE 8255
MODE 2 (STROBED BIDIRECTIONAL INPUT / OUTPUT)
⮚ Input Operations:
⮚ STB’ - (Strobe Input): A “low” on this input loads data into
the input latch.
⮚ IBF - (Input Buffer Full F/F): A “high” on this output indicates
⮚ that data has been loaded into the input latch.
⮚ INTE 2 - (The INTE flip-flop associated with IBF): Controlled
by bit set/reset of PC4.
⮚ INTR - (Interrupt Request): A high on this output can be used
to interrupt the CPU for both input or output operations.
⮚ Output Operations:
⮚ OBF’ - (Output Buffer Full):The OBF output will go “low” to indicate
that the CPU has written data out to port A.
⮚ ACK’ - (Acknowledge): A “low” on this input enables the three-state
output buffer of port A to send out the data. Otherwise, the
output buffer will be in the high impedance state.
⮚ INTE 1 - (The INTE flip-flop associated with OBF): Controlled by bit
set/reset of PC4.
 8259
Programmable Interrupt
Controller-- 1
 CONTENTS
⚫Introduction
⚫Processing Interrupts
⚫8086/88 Hardware Interrupt Pins
⚫Interrupt Flag
⚫8259
⚫Pin Description
⚫Block Diagram
⚫Interfacing
⚫Operation
 INTRODUCTION
⮚ An interrupt is an event which informs the
CPU that its service (action) is needed.
⮚ Sources of interrupts:
⮚ internal fault (e.g.. divide by zero, overflow)
⮚ Software
⮚ external hardware : maskable, nonmaskable
⮚ reset
 PROCESSING INTERRUPTS
⮚ When an interrupt is executed, the
microprocessor:
⮚ finishes executing its current instruction (if any).
⮚ saves (PUSH) the flag register, IP and CS register in
the stack.
⮚ goes to a fixed memory location.
⮚ reads the address of the associated ISR.
⮚ Jumps to that address and executes the ISR.
⮚ gets (PULL) the flag register, CS:IP register from the
stack.
⮚ continues executing the previous job (if any).
 8086/88 Hardware Interrupt Pins
⮚ INTR: Interrupt Request.
⮚ Input signal into the CPU
⮚ If it is activated, the CPU will finish the current
instruction and respond with the interrupt acknowledge
operation
⮚ Can be masked (ignored) thru instructions CLI and STI
⮚ NMI: NonMaskable interrupt.
⮚ Input signal
⮚ Cannot be masked or unmasked thru CLI and STI
⮚ Examples of use: power frailer. Memory error
⮚ INTA: Interrupt Acknowledge.
⮚ Output signal
 INTERRUPT FLAG
⮚ IF (Interrupt Enable Flag) D9: used to mask any
hardware interrupt that may come in from the
INTR pin.
⮚ When IF=0, all hardware interrupt requests
through INTR are masked.
⮚ This has no effect on interrupts coming from the
NMI pin or “INT nn” instructions.
⮚ CLI sets IF to 0, STI sets IF to 1.
 INT n and ISR
⚫n is multiplied by 4
⚫In the address “4n” the offset address the ISR is
found.
⚫Example:Intel has set aside INT 2 for the NMI
interrupt.
⚫Whenever the NMI pin is activated, the CPU
jumps to physical memory location 00008 to
fetch the CS:IP of the interrupt service routine
associated with the NMI.
 8259
⮚ 8259 is Programmable Interrupt Controller (PIC)
⮚ It is a tool for managing the interrupt requests.
⮚ 8259 is a very flexible peripheral controller chip:
⮚ PIC can deal with up to 64 interrupt inputs
⮚ interrupts can be masked
⮚ various priority schemes can also programmed.
⮚ Originally (in PC XT) it is available as a separate IC
⮚ Later the functionality of (two PICs) is in
the motherboards chipset.
⮚ In some of the modern processors, the functionality of
the PIC is built in.
 PIN DESCRIPTION
⚫8-bit bi-directional data bus, one address line is
needed, PIC has two control registers to be
programmed, you can think of them as two output
ports or two memory location.
⚫The direction of data flow is controlled by RD and
WR.
⚫CS is as usual connected to the output of the
address decoder.
⚫Interrupt requests are output on INT which is
connected to the INTR of the processor. Int.
acknowledgment is received by INTA.
⚫IR0-IR7 allow 8 separate interrupt requests to be
inputted to the PIC.
⚫sp/en=1 for master , sp/en=0 for slave.
⚫CAS0-3 inputs/outputs are used when more than
BLOCK DIAGRAM
Interfacing the PIC to 386 and 486
All interrupt requests pass through Interrupt Request
Register & Interrupt Mask Register
TWO CASCADED PICS
 OPERATION
⮚ PIC is to be initialized and programmed to control its
operation.
⮚ The operation in simple words:
⮚ When an interrupt occurs , the PIC determines the highest
priority, activates the processor via its INTR input, and sends the
type number onto the data bus when the processor acknowledges
the interrupt.
⮚ Priority:
⮚ What is used in PC is fully nested mode. That is the lowest
numbered IRQ input has highest priority. Lower priority
interrupts will not be forwarded to the processor until the higher
priority interrupts have been serviced.
 BASIC DMA CONCEPT
🞆 Direct memory access (DMA) is a
feature of modern computer systems that
allows certain hardware subsystems to
read/write data to/from memory without
microprocessor intervention, allowing the
processor to do other work.
🞆 Used in disk controllers, video/sound
cards etc, or between memory
locations.
🞆 Typically, the CPU initiates DMA transfer,
does other operations while the transfer is
in progress, and receives an interrupt from
 BASIC DMA TERMINOLOGY
⚫DMA channel: system pathway used by
a device to transfer information directly
to and from memory.There are usually 8
in a computer system
⚫DMA controller: dedicated hardware
used for controlling the DMA operation
⚫Single-cycle mode: DMA data transfer
is done one byte at a time
⚫Burst-mode: DMA transfer is finished
when all data has been moved.
 DMA PINS AND TIMING
⮚ x86 Interrupt Pins
⮚ HOLD: DMA request.
⮚ 🞄 Sampled in the middle of any clocking cycle
⮚ HLDA: DMA acknowledge signal.
⮚ 🞄 The address, data and control buses are set to
high-Z, so the I/O devices can control the system
bus 1 2 3 4 5 6 7 8 9
CLK

HOL

HLDA
 DMA on the 8086
Microprocessor
⚫ The I/O device asserts the appropriate DRQ signal for the channel.
⚫ The DMA controller will enable appropriate channel, and ask the
CPU to release the bus so that the DMA may use the bus. The DMA
requests the bus by asserting the HOLD signal which goes to
the CPU.
⚫ The CPU detects the HOLD signal, and will complete executing the
current instruction. Now all of the signals normally generated
by the CPU are placed in a tri-stated condition (neither high or
low) and then the CPU asserts the HLDA signal which tells the
DMA controller that it is now in charge of the bus.
⚫ The CPU may have to wait (hold cycles).
⚫ DMA activates its -MEMR, -MEMW, -IOR, -IOW output signals,
and the address outputs from the DMA are set to the target address,
which will be used to direct the byte that is about to
transferred to a specific memory location.
36
 DMA on the 8086
Microprocessor
⚫ The DMA will then let the device that requested the DMA transfer
know that the transfer is commencing by asserting the -DACK
signal.
⚫ The peripheral places the byte to be transferred on the bus Data
lines.
⚫ Once the data has been transferred, The DMA will de-assert the -
DACK2 signal, so that the FDC knows it must stop placing data on
the bus.
⚫ The DMA will now check to see if any of the other DMA channels
have any work to do. If none of the channels have their DRQ lines
asserted, the DMA controller has completed its work and will
now tri-state the - MEMR, -MEMW, -IOR, -IOW and address
signals.
⚫ Finally, the DMA will de-assert the HOLD signal. The CPU sees
this, and de-asserts the HOLDA signal. 37Now the CPU resumes
 EXAMPLE
⚫Assuming that a DMA initialization has an
overhead of 10 cycles, while a CPU transfer
to/from memory requires 4 cycles (no wait states
required), compare a DMA and a CPU transfer
from one memory location to another of
◦ One byte of data
◦ A block of 1Kbytes in burst mode
◦ A block of 64Kbytes in burst mode

38
 THE 8237 DMA CONTROLLER
🞆 Supplies memory and I/O with control
signals and addresses during DMA transfer
🞆 4-channels (expandable)
⚫ 0: DRAM refresh
⚫ 1: Free
⚫ 2: Floppy disk controller
⚫ 3: Free
🞆 1.6MByte/sec transfer rate
🞆 64 KByte section of memory
address capability with single
programming
 8237 PINS
⮚ CLK: System clock
⮚ CS΄: Chip select (decoder output)
⮚ RESET: Clears registers, sets mask register
⮚ READY: 0 for inserting wait states
⮚ HLDA: Signals that the μp has relinquished buses
⮚ DREQ3 – DREQ0: DMA request input for each channel
⮚ DB7-DB0: Data bus pins
⮚ IOR΄: Bidirectional pin used during programming
⮚ and during a DMA write cycle
⮚ IOW΄: Bidirectional pin used during programming and during a
DMA read cycle
⮚ EOP΄: End of process is a bidirectional signal used as input to terminate a DMA
process or as output to signal the end of the DMA transfer
⮚ A3-A0:Address pins for selecting internal registers
⮚ A7-A4: Outputs that provide part of the DMA transfer address
⮚ HRQ: DMA request output
⮚ DACK3-DACK0: DMA acknowledge for each channel.
⮚ AEN:Address enable signal
⮚ ADSTB:Address strobe
⮚ MEMR΄: Memory read output used in DMA read cycle
⮚ MEMW΄: Memory write output used in DMA write cycle.
8237 PIN DIAGRAM

41
A 8237 DMA application

DMA ARCHITECTURE
 8237 REGISTERS
⮚ CAR (Current Address Register): holds
the 16-bit memory address used for the
DMA transfer (one for each channel),
either incremented or decremented
during the operation.
⮚ CWCR (Current Word Count Register):
Programs a channel for the number of
bytes (up to 64K) transferred during a
DMA operation.
⮚ BA (Base Address) and WC (Word).
⮚ MR (Mode Register):

⮚ Programs the mode of

operation for a
channel (one for each
channel).

44
⚫MR (Mask
Register):

⚫SR (Status
Register):
Shows the
status of each
8237 SOFTWARE COMMANDS
 8237 SOFTWARE COMMANDS
🞆 Clear First/Last Flip-Flop - This command is executed
prior to writing or reading new address or word count
information to the 82C37. This command initializes
the flipflop to a known state (low byte first) so that
subsequent accesses to register contents by the
microprocessor will address upper and lower bytes in
the correct sequence.
🞆 Set First/Last Flip-Flop - This command will set the flip-
flop to select the high byte first on read and write
operations to address and word count registers.
🞆 Master Clear - This software instruction has the same
effect as the hardware Reset. The Command, Status,
Request, and Temporary registers, and Internal First/Last
Flip-Flop and mode register counter are cleared and the
Mask register is set. The 82C37A will enter the idle
cycle.
🞆 Clear Mask Register - This command clears the mask
bits of all four channels, enabling them to accept
DMA requests.
🞆 Clear Mode Register Counter - Since only one
8237 block diagram