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Memory Originated

Memory interleaving is a technique that enhances memory access performance by distributing memory addresses across multiple banks, allowing simultaneous read/write operations. Cache memory, a high-speed storage located between the CPU and main memory, stores frequently accessed data to reduce wait times and improve system performance. Various cache mapping techniques and replacement algorithms are employed to optimize data retrieval and manage limited cache capacity.
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0% found this document useful (0 votes)
15 views28 pages

Memory Originated

Memory interleaving is a technique that enhances memory access performance by distributing memory addresses across multiple banks, allowing simultaneous read/write operations. Cache memory, a high-speed storage located between the CPU and main memory, stores frequently accessed data to reduce wait times and improve system performance. Various cache mapping techniques and replacement algorithms are employed to optimize data retrieval and manage limited cache capacity.
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MODULE 5

MEMORY INTERLEAVING
• Memory interleaving is a technique used in computer systems
to improve the performance of memory accesses, particularly
in systems with multiple memory modules (like RAM). The
primary goal is to increase data throughput and minimize
latency by distributing memory addresses across multiple
memory banks or modules.
• In simpler terms, memory interleaving divides memory into
multiple "banks," and data is stored in such a way that
consecutive memory locations are spread across these banks.
This allows the system to read from or write to multiple
memory banks simultaneously, thereby improving overall
system performance.
• How it works:
• Address Mapping: Memory addresses are mapped in such a
way that sequential addresses (or groups of addresses) are
assigned to different memory banks.
• For example, in a two-bank system:
– Memory address 0x0000 goes to bank 0
– Memory address 0x0001 goes to bank 1
– Memory address 0x0002 goes to bank 0
– Memory address 0x0003 goes to bank 1
– And so on…
• Parallel Access: Because each bank can operate
independently, the system can read or write to two or more
banks at the same time, which increases the speed of
memory operations, especially for sequential data accesses.
• Types of Memory Interleaving:
• Low-order interleaving: The least significant bits of
the memory address are used to determine the
bank. This type of interleaving is useful for systems
that frequently access sequential memory
locations.
• High-order interleaving: The most significant bits
of the address are used to determine the bank.
This type is often used when the system accesses
non-sequential data.
• Block interleaving: A combination of low-order and
high-order interleaving where large blocks of data
are distributed across memory banks.
• Example in the Context of Computer Systems:
• Suppose a computer has 4 memory banks. With
interleaving, the system can read or write to multiple
banks in parallel. If you're loading a large file or
processing large arrays, this parallelism allows the
system to access different parts of the data at once,
which improves performance, especially in multi-core
systems or when performing heavy computational
tasks like graphics rendering or scientific simulations.
• In conclusion, memory interleaving helps optimize
the use of available memory resources, improving
the performance of a system by enabling parallel
access to multiple memory locations.
• NOTE- I HAVE EXPLAINED THE CONCEPT OF
MEMORY INTERLEAVING ALREADY IN THE
CLASS IN VERY EASY WAY . THEN YOU SHOULD
STUDY THIS TOPIC FROM MY NOTES.
CONCEPT OF HIRARCHICAL MEMORY
ORGANIZATION
• THIS TOPIC IS ALREADY IN YOUR ASIGNMENT
COPY.
CACHE MEMORY
• Cache memory is a small, high-speed memory unit located between the CPU
and main memory, designed to store frequently accessed data and instructions
for faster retrieval, improving overall system performance.
• Here's a more detailed explanation:
• Purpose:
• Cache memory acts as a buffer, holding copies of data that the CPU is likely to
need soon, allowing it to access that data much faster than retrieving it from
the slower main memory (RAM).
• Location:
• It's situated on the processor chip or between the processor and main memory.
• Speed and Capacity:
• Cache memory is significantly faster but has a much smaller capacity than main
memory.
• Levels:
• Modern systems often use a hierarchical cache structure with multiple levels
(L1, L2, L3), where L1 is the fastest and smallest, and L3 is the slowest and
largest.
• Types of Cache Memory:
• L1 Cache: Built into the CPU, extremely fast, and stores
recently used instructions or data.
• L2 Cache: Slightly slower and larger than L1, often
located on the processor chip.
• L3 Cache: The largest and slowest of the cache levels,
typically located on the main board.
• Benefits:
• Reduced CPU Wait Time: By providing quick access to
frequently used data, cache memory minimizes the time
the CPU spends waiting for data from main memory.
• Improved System Performance: Faster data access
translates to faster overall system performance.
• Principle of Locality:
• Cache memory relies on the principle of locality
of reference, which states that programs tend to
access the same data or nearby data locations
repeatedly.
• Cache Hit vs. Cache Miss:
• Cache Hit: When the CPU finds the data it
needs in the cache, it's called a cache hit, and
the data is retrieved quickly.
• Cache Miss: If the data isn't in the cache, it's a
cache miss, and the CPU must retrieve it from
main memory, which is slower.
CACHE SIZE VS. BLOCK SIZE
• In computer architecture, cache size refers to the total
amount of data a cache can hold, while block size (also
called cache line) is the smallest unit of data transferred
between the cache and main memory.
• Here's a more detailed explanation:
• Cache Size:
• Represents the total capacity of the cache memory,
measured in bytes (e.g., 32KB, 64KB, 1MB).
• A larger cache size can hold more data, potentially leading
to more frequent cache hits and improved performance.
• Block Size (Cache Line):
• Defines the granularity at which data is transferred between the
cache and main memory.
• When a cache miss occurs, the entire block (cache line)
containing the requested data is fetched from main memory and
stored in the cache.
• Typical block sizes are 64 bytes on modern systems.
• Relationship:
• Cache size is determined by the number of blocks (lines) the
cache can hold and the block size itself.
• For example, a 64KB cache with a 64-byte block size can hold
1024 blocks (64KB / 64 bytes).
• The block size is a key factor in how efficiently the cache utilizes
spatial locality, where data accessed near each other in memory
is likely to be accessed together.
• Example:
• Consider a 1MB cache with a 64-byte block
size.
• This means the cache can hold 16,384 blocks
(1MB / 64 bytes).
• When the CPU needs data, it checks if the
data is in the cache (cache hit).
• If not (cache miss), the entire block containing
the data is fetched from main memory and
stored in the cache.
• Basic elements of cache design:
• • Size
• • Mapping function
• • Replacement algorithm
• • Write policy
• • Block size
• • Number of caches
• Cache-Mapping Function :
• The transformation of data from main memory to
cache memory is referred to as memory mapping
process.
• This is one of the functions performed by the
memory management unit (MMU).
• Because there are fewer cache lines than main
memory blocks, an algorithm is needed for
mapping main memory blocks into cache lines.
• There are three different types of mapping
functions in common use and are direct,
associative and set associative.
• Cache mapping refers to a technique using
which the content present in the main
memory is brought into the memory of the
cache. Three distinct types of mapping are
used for cache memory mapping.
• Process of Cache Mapping
• The process of cache mapping helps us define
how a certain block that is present in the main
memory gets mapped to the memory of a
cache in the case of any cache miss.
• In simpler words, cache mapping refers to a
technique using which we bring the main
memory into the cache memory. Here is a
diagram that illustrates the actual process of
mapping:
• Important Note:
• The main memory gets divided into multiple
partitions of equal size, known as the frames
or blocks.
• The cache memory is actually divided into
various partitions of the same sizes as that of
the blocks, known as lines.
• The main memory block is copied simply to
the cache during the process of cache
mapping, and this block isn’t brought at all
from the main memory.
• Techniques of Cache Mapping
• One can perform the process of cache
mapping using these three techniques given
as follows:
• 1. K-way Set Associative Mapping
• 2. Direct Mapping
• 3. Fully Associative Mapping
• Associative Mapping:
• In this type of mapping, the associative memory is
used to store content and addresses of the
memory word. Any block can go into any line of
the cache. This means that the word id bits are
used to identify which word in the block is needed,
but the tag becomes all of the remaining bits. This
enables the placement of any word at any place in
the cache memory. It is considered to be the
fastest and the most flexible mapping form.
• This mapping method is also known as fully
associative mapping.
• Direct Mapping :
• This is the simplest among the three techniques. Its
simplicity stems from the fact that it places an incoming
main memory block into a specific fixed cache block
location.
• The main advantage of the direct-mapping technique is
its simplicity in determining where to place an incoming
main memory block in the cache.
• The main disadvantage is the inefficient use of the
cache. This is because a number of main memory blocks
may compete for a given cache block even if there exist
other empty cache blocks. This disadvantage should
lead to achieving a low cache hit ratio.
• Set-Associative Mapping:
• This is a compromise between direct and
associative mapping, dividing the cache into
sets.
• A main memory block can be mapped to any
line within a specific set.
• It improves on direct mapping by reducing the
chance of cache thrashing.
CACHE REPLACEMENT ALGORITHM
• Cache replacement algorithms, also known as
cache replacement policies, are strategies
used to determine which data to remove from
a cache when it's full and a new piece of data
needs to be stored. Common algorithms
include FIFO (First-In, First-Out), LRU (Least
Recently Used), and LFU (Least Frequently
Used).
• Why are Cache Replacement Algorithms Needed?
• Limited Cache Size:
• Caches have a limited capacity, so when they
become full, a mechanism is needed to decide
which data to discard to make space for new data.
• Performance Optimization:
• Effective cache replacement algorithms aim to
minimize the number of cache misses, which are
instances where the requested data is not found
in the cache and must be fetched from slower
memory.
• Common Cache Replacement Algorithms:
• FIFO (First-In, First-Out):
• How it works: Replaces the oldest data in the
cache, regardless of how frequently it's been
used.
• Pros: Simple to implement.
• Cons: Can evict frequently accessed data if it
was added earlier, leading to many cache
misses.
• LRU (Least Recently Used):
• How it works: Replaces the data that has been accessed least
recently, assuming that data accessed in the past is less likely to
be needed soon.
• Pros: Generally performs well in practice.
• Cons: Requires tracking access times, which can add to the
overhead.
• LFU (Least Frequently Used):
• How it works: Replaces the data that has been accessed the
least number of times, assuming that data accessed less
frequently is less likely to be needed soon.
• Pros: Can be effective in scenarios where some data is accessed
much more frequently than others.
• Cons: Requires tracking access frequencies, which can add to
the overhead.
• Other Algorithms:
• Optimal (OPT): A theoretical algorithm that
replaces the page that will not be used for the
longest time in the future (not practically
implementable).
• Random: Randomly selects a page to replace.

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