MOUNT ZION COLLEGE OF ENGINEERING AND

TECHNOLOGY

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

EE3404
MICROPROCESSOR AND MICROCONTROLLER

Total no of Students : 32
Prepared By : R.RAMANATHAN, AP/EEE
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 DEPARTMENT OF
ELECTRICAL AND ELECTRONICS ENGINEERING

VISION

To raise high-quality Electrical and Electronics engineers with a solid

foundation in their chosen field, with exposure to the latest developments, who can
think out of the box and are innovative through focused teaching, systematic
learning and hands-on research activities.
MISSION

 To impart quality education by creating an excellent academic environment for

students.

 Carry out quality research involving faculty and students in the emerging fields
of Electrical and Electronics Engineering.

 To inculcate moral and ethical values among faculty and students.

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 OBJECTIVES

• To study the addressing modes & instruction set of 8085 &8051

• To develop skills in simple program writing in assembly languages.

• To introduce commonly used peripheral/interfacing ICs.

• To study and understand typical applications of micro-processors.

• To study and understand the typical applications of micro-controllers

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 EXPECTED OUTCOME
CO1: Ability to write assembly language program for microprocessor and microcontroller
CO2: Ability to design and implement interfacing of peripheral with microprocessor and
microcontroller
CO3: Ability to analyze, comprehend, design and simulate microprocessor based systems used for
control and monitoring.
CO4: Ability to analyze, comprehend, design and simulate microcontroller based systems used for
control and monitoring.
CO5: Ability to understand advanced architecture evolving microprocessor field
CO6: Ability to appreciate advanced architecture evolving microprocessor field

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 EE3404
MICROPROCESSOR
AND MICROCONTROLLER
1. INTRODUCTION TO 8085 ARCHITECTURES

2. 8085 INSTRUCTION SET AND PROGRAMMING

3. INTERFACING BASICS AND ICS

4. INTRODUCTION TO 8051 MICROCONTROLLERS

5. INTRODUCTIONTO RISC BASED ARCHITECTURE

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 UNIT -1
INTRODUCTION TO 8085 ARCHITECTURES
1.1 FUNCTIONAL BLOCK DIAGRAM

1.2 MEMORY INTERFACING

1.3 I/O PORTS

1.4 DATA TRANSFER CONCEPTS

1.5 TIMING DIAGRAM

1.6 INTERRUPT STRUCTURE.

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TOPICS DISCUSSED IN PREVIOUS CLASS

1.3 I/O PORTS

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TOPICS GOING TO BE DISCUSSED IN TODAY’S
SESSION

1.4 DATA TRANSFER

CONCEPTS

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 1.4 DATA TRANSFER CONCEPTS

In a microprocessor based system or in a computer data transfer takes

place between two devices such as
1) Between microprocessor and memory
2) Between memory and I/O device
3) Between microprocessor and I/O devices
A microprocessor based system or a computer may have several I/O devices
of different speed.

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 1.4 DATA TRANSFER CONCEPTS
Data transfer schemes

Programmed data
transfer scheme DMA Scheme

Synchronous data transfer scheme Brust mode of DMA data transfer

Asynchronous data transfer
Cycle stealing technique of DMA data
scheme
Interrupt driven data transfer transfer
scheme
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 1.4 DATA TRANSFER CONCEPTS
Programmed data transfer schemes
 These schemes are controlled by the CPU. Data are transferred from
an I/O device to the CPU or vice versa.
 Data are transferred under the control of programs which reside in
the memory. These programs are executed by the CPU when an I/O
 Device are ready to transfer data.
 The microprocessor executes the program to transfer data. This
Scheme is suitable for transferring small amount of data
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 1.4 DATA TRANSFER CONCEPTS
Synchronous type of data transfer
• Synchronous type of data transfer can be used when the speed of
the I/O devices matches with the speed of the 8085
microprocessor.
• So we need common clock pulse for established the
synchronization between I/O device and microprocessor.
• This common clock pulse synchronizes the microprocessor and
the I/O devices.

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 1.4 DATA TRANSFER CONCEPTS
• In synchronous type of data transfer scheme, it has matching of
the speed with I/O devices.
• So it does not have to wait for the availability of the data.
• As soon as the microprocessor issues a signal, it immediately
sends data for the transfer .

The asynchronous type data transfer

 The asynchronous data transfer method is used when the speed of
the I/O devices is slower than the speed of the microprocessor.
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 1.4 DATA TRANSFER CONCEPTS
 Because of the mismatch of the speed, the internal timing of the
I/O device is independent from the microprocessor.
 That is why those two units can said to be asynchronous to each
other.
 The asynchronous data transfer is normally implemented using
‘handshaking’ mode.
 In the handshaking mode some signals are exchanged between
the I/O device and microprocessor before the data transfer takes
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 1.4 DATA TRANSFER CONCEPTS
place.
 Now look at the flow chart bellow which can describe the total
process step wise.

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 1.4 DATA TRANSFER CONCEPTS
Interrupt Driven I/O Data Transfer
 The interrupt driven I/O data transfer method is very efficient.
Because no microprocessor time is wasted in waiting for an I/O
device to be ready.
 After checking the I/O device is ready or not. In this interrupt driven
I/O data transfer method, the I/O device informs the
microprocessor for the data transfer.
 And This can achieved by interrupting the microprocessor.
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 1.4 DATA TRANSFER CONCEPTS
 As we know, the interrupt is hardware facilities provided on
the microprocessor.
Single Interrupt System
When only one interrupt line is available with the microprocessor. And
several I/O devices has to connect. Then the method will known as
Single Interrupt System.
Multi Interrupt System
When the microprocessor has several interrupt terminals. And one I/O
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 1.4 DATA TRANSFER CONCEPTS
device has to connect in each interrupt terminal.
• Then it known as multi interrupt system. Now some important thing
we should remember.
• In this scheme, the number of I/O devices to be connected to the
interrupt lines should be equal to or less than the number of
interrupt terminals.
• In this way one device can connected to each level of interrupt.

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 1.4 DATA TRANSFER CONCEPTS
• So when a device interrupts the microprocessor, it immediately
knows which device has interrupted.
• Such an interrupt scheme also known as vectored interrupt.

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 1.4 DATA TRANSFER CONCEPTS
Direct Memory Access Controller
DMA controller is a hardware unit that allows I/O devices to
access memory directly without the participation of the
processor.
1.Whenever an I/O device wants to transfer the data to or
from memory, it sends the DMA request (DRQ) to the DMA
controller. DMA controller accepts this DRQ and asks the CPU
to hold for a few clock cycles by sending it the Hold request
(HLD).
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 1.4 DATA TRANSFER CONCEPTS
2.CPU receives the Hold request (HLD) from DMA controller
and
relinquishes the bus and sends the Hold acknowledgement (HLDA) to DMA
controller.
3. After receiving the Hold acknowledgement (HLDA), DMA controller
acknowledges I/O device (DACK) that the data transfer can be performed
and DMA controller takes the charge of the system bus and transfers the
data to or from memory.
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 1.4 DATA TRANSFER CONCEPTS

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 1.4 DATA TRANSFER CONCEPTS
1.Burst Mode:
 Here, once the DMA controller gains the charge of the
system bus, then it releases the system bus only
after completion of data transfer.
 Till then the CPU has to wait for the system buses.
2.Cycle Stealing Mode:
• In this mode, the DMA controller forces the CPU to stop
its operation and relinquish the control over the
bus for a short
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 1.4 DATA TRANSFER CONCEPTS
term to DMA controller.
• After the transfer of every byte, the DMA
controller releases the bus and then again requests for
the system bus.
• In this way, the DMA controller steals the clock cycle for
transferring every byte.
3.Transparent Mode:
 Here, the DMA controller takes the charge of system bus
only if
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 1.4 DATA TRANSFER CONCEPTS
the processor does not require the system bus.

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 1.4 DATA TRANSFER CONCEPTS
Advantages:
1.Transferring the data without the involvement of the
processor will speed up the read-write task.
2.DMA reduces the clock cycle requires to read or write a
block of data.
3.Implementing DMA also reduces the overhead of the
processor.
Disadvantages
4.As it is a hardware unit,
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 1.4 DATA TRANSFER CONCEPTS
in the system.
2.Cache coherence problem can occur while using DMA
controller.

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 1.4 DATA TRANSFER CONCEPTS
REFERENCE VIDEOS

https://www.bing.com/videos/riverview/relatedvideo?&q=D
MA++DATA+TRANSFER+CONCEPTS+IN+MICROPROCESSOR+LIV
E+IMAGES&&mid=EF1FE0544DBFB3A24B5EEF1FE0544DBFB3
A24B5E&&FORM=VRDGAR

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 THANK YOU

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