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Lecture 9b - Fetch Decode Execute Cycle

The document outlines a lecture on computer architecture focusing on the Fetch Decode Execute cycle, detailing the roles and functions of the CPU. It describes the instruction cycle steps, including instruction fetch, decode, data fetch, execution, and result return, along with CPU structures like pipelining and superscalar execution. Additionally, it emphasizes the importance of CPU clock speed in measuring performance.

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aidaraihanah
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21 views

Lecture 9b - Fetch Decode Execute Cycle

The document outlines a lecture on computer architecture focusing on the Fetch Decode Execute cycle, detailing the roles and functions of the CPU. It describes the instruction cycle steps, including instruction fetch, decode, data fetch, execution, and result return, along with CPU structures like pipelining and superscalar execution. Additionally, it emphasizes the importance of CPU clock speed in measuring performance.

Uploaded by

aidaraihanah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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5604TECYPC

Computer Architecture

Lecture 9
Fetch Decode Execute
Cycle
Prepared by: Aida Raihanah
Date Time Tentative Lessons
28/3/2025 9 - 10.30 AM Addressing Modes

11 - 12.30 PM Fetch Decode Execute Instruction Cycle

11/4/2025 9 - 10.30 AM Introduction to computer systems software and input / output


devices

11 - 12.30 PM Process, threads and resources management

18/4/2025 9 - 10.30 AM Scheduling algorithms

11 - 12.30 PM Tutorials and Revisions


Central Processing Unit (CPU) /
Processor
● CPU controls everything the computer does (brain of computer).
● CPU is the electronic circuitry that performs basic arithmetic logic controlling and
input output operations specified by a computer program.
● CPU follows instructions that are stored in the computer's memory, which is like
the computer's long-term storage.
● However, getting information from memory is relatively slow.
● To speed things up, the CPU has its own small, very fast storage areas called
registers. It keeps the most important information and temporary results
that the CPU needs to access very quickly.
● The purpose of the CPU is to fetch, decode and execute instructions – billions of
times a second.
CPU Structures

Feature Pipeline Superscalar

Overlapping the stages of execution Executing multiple independent


Concept
of different instructions. instructions simultaneously.

Multiple instructions are fetched and decoded,


Instruction execution is broken down into
Execution then executed simultaneously using multiple
stages (fetch, decode, execute, etc.).
execution units.

Improves throughput by allowing multiple Provides a greater performance boost than


Performance instructions to be in different stages of pipelining by executing multiple instructions
execution at the same time. concurrently.

Increases complexity compared to non- Increases complexity significantly compared to


Complexity
pipelined CPUs. pipelined CPUs.
Instruction Cycle

Instruction Fetch (IF)


STEP
1

Instruction Decode (ID)


STEP
2

Data Fetch (DF)


STEP
3

Instruction Execution (EX)


STEP
4

Result Return (RR)


STEP
5
Instruction Fetch (IF)
● The program counter is checked for the address of the next instruction
to be executed.
● The address is then copied into the Memory Address Register (MAR).
● The address is sent along the address bus to main memory, where it
waits to receive a signal from the control bus.
● The control unit sends a signal along the control bus to main memory.
● The contents stored in memory can be sent along the data bus to the
memory data register.
● The data received from memory by the memory data register is copied
into the current instruction register.
● Then, increment the contents of the program counter so the address it
contains points to the next instruction to be executed.
Instruction Decode (ID)
● The instruction in the current instruction register is inspected and decoded to
work out what needs to be done.
● The instruction is made up of 2 parts:
○ Opcode – what to do
○ Operand – what to do it to
● The operand could contain the actual data or the address where the data is.
Data Fetch (DF)
● Send the address to the memory address register (MAR).
● Control unit sends a read signal along the control bus to main memory.
● The contents stored in memory can be sent along the data bus to the
memory data register.
Instruction Execution (EX)
● The contents of the memory data register are copied to the
accumulator.
● The instruction is carried out, it could be:
○ Going back to main memory and fetching data
○ Performing a calculation
○ Storing information back in main memory
● Depending on the instruction, data may end up being copied into the ALU
and/or the accumulator.
Return Result (RR)
● The Result Return stage is responsible for taking the result from
the ALU and writing it to that destination address.
● Once the result is stored, the cycle begins again.
● The program counter is checked for the address of the next
instruction.
CPU Clock Speed
● CPU clock speed / Clock rates / CPU frequency
● It is a measure of how many clock cycles a CPU can perform in 1
second
● Measure in Hertz (1 cycle per second)
4,000,000,
000
CPU can perform four billion clock cycles in one second
QUIZ
https://kahoot.it/

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