Module IV

The Processor - Introduction, Logic design conventions, Building a data

path, A simple implementation scheme, An overview of pipelining -
Pipelined data path and control – Structural hazards - Data hazards -
Control hazards
Processor- Introduction

The performance of a computer is determined by three key factors:

• Instruction count,
• Clock cycle time, and
• Clock cycles per instruction (CPI).
Processor- Introduction

• Instruction count: Determined by compiler and the instruction set

architecture

• Clock cycle time and CPI: Determined by the implementation of the

processor, CPU hardware
MIPS Architecture
• Stands for Microprocessor without Interlocked Pipelined Stages.

• A family of instruction set architectures developed by MIPS Computer

Systems, now MIPS Technologies, based in the United States.

• There are multiple versions of MIPS: including MIPS I, II, III, IV, and V

• The early MIPS architectures were 32-bit; 64-bit versions were

developed later.
 Data Path
• Datapath: portion of the processor that contains hardware necessary to
perform operations required by the processor.

• Datapath designed to support data transfers required by instructions

• Control: portion of the processor (also in hardware) that tells the

datapath what needs to be done (the brain)

• datapath and control are the two components that come together to be
collectively known as the processor
Data Path
• Datapath consists of the functional units of the processor.

1. Elements that hold data.

• Program counter, register file, instruction memory, etc.
2. Elements that operate on data.
• ALU, adders, etc.
3. Buses for transferring data between elements.
Components Involved
• We will look at the data path elements needed by every instruction:

• Instruction Memory: provides read-access to the instructions of a

program and, given an address as input,
• supplies the corresponding instruction at that address.
Components Involved
• Program counter:32 bit register that hold the address of current instruction to be
fetched.
• Normally PC increments sequentially except for branch instructions

• Adder : The adder is responsible for incrementing the PC to hold the address of the
next instruction.
• It takes two input values, adds them together and outputs the result
Components Involved
• Register File:A collection of registers in which any register can be read
or written by specifying the address of the register.
• Arithmetic & logical instructions are R type
• These type of instructions have 3 registers:2 source & one destination
Register.

• Data Memory: Data memory has to be read on load instruction and

written on store instruction
Logic Design Conventions
• The datapath elements in the MIPS implementation belongs to any one
of the two different types of logic elements:
1. elements that operate on data values (combinational elements)
2. elements that contain state (state elements)

Combinational elements:
• Their outputs depend only on the current input.
• The ALU is an example of combinational element.
• Given the same input, a combinational element always produces the
same output because it has no internal storage.
Logic Design Conventions
State elements:
• An element contains state if it has some internal storage.
• The instruction and data memories, as well as the registers, are all
examples of state elements.
• A state element has at least two inputs and one output. The required
inputs are the data value to be written into the element and the clock.
• The clock is used to determine when the state element should be written:
• Logic components that contain state are also called sequential because
their outputs depend on both their input and the contents of the internal
state.
Basic MIPS implementation

• To showcase the process of creating a datapath and designing a

control, we will be using a subset of the MIPS instruction set.

• Memory-reference instructions: load word (lw) and store word (sw)

• Arithmetic-logical instructions: add, sub, AND, OR, and sll(shift left)
• Branch instructions: branch on equal (beq) and jump (j)
An Overview of MIPS
Implementation
• What needs to be done to implement the instructions is the same,
independent of the exact class of instruction.

• For every instruction, the first two steps are identical:

1. Send the program counter (PC) to the memory that contains the
code and fetch the instruction from that memory.

2. Read one or two registers, using fields of the instruction to select

the registers to read. For the load word instruction, we need to read
only one register, but most other instructions require reading two
registers.
An Overview of MIPS
Implementation
• Remaining actions required to complete the instruction depend on
the instruction class.

• For each of the three instruction classes (memory-reference,

arithmetic-logical, and branches), the actions are largely the same,
independent of the exact instruction

• All instructions except jump, use the arithmetic-logical unit (ALU) after
reading the registers.
An Overview of MIPS
Implementation
• The memory-reference instructions use the ALU for an address
calculation.

• The arithmetic-logical instructions uses ALU for the operation

execution.

• Branch Instructions uses ALU for comparison.

An Overview of MIPS
Implementation
• Actions required to complete various instruction classes differ after ALU Usage.

• A memory-reference instruction will need to access the memory either to read data for a
load or write data for a store.

• An arithmetic-logical or load instruction must write the data from the ALU or memory back
into a register.

• For a branch instruction, we may need to change the next instruction address based on the
comparison.

• Otherwise the PC should be incremented by 4 to get the address of the next instruction.(32
bit word)
Basic MIPS implementation

• To execute an instruction the basic steps involved are:

1. Fetch instruction
2. Increment program counter by 4 to point to next instruction
3. Execute instruction
An Overview of MIPS
Implementation

An abstract view of the implementation of the MIPS subset showing the major functional units
and the major connections between them.
An Overview of MIPS
Implementation
• All instructions start by using the program counter to supply the instruction
address to the instruction memory.

• After the instruction is fetched, the register operands used by an instruction

are specified by fields of that instruction.

• Once the register operands have been fetched, they can be operated on to
• compute a memory address(for load & store) or
• compute an arithmetic result (for an integer arithmetic-logical instruction),
• or a compare(for branch)
 An Overview of MIPS
Implementation
• If the instruction is an arithmetic-logical instruction, the result from
the ALU must be written to a register.

• If the operation is a load or store, the ALU result is used as an address

to either store a value from the registers or load a value from memory
into the registers.

• The result from the ALU or memory is written back into the register.
An Overview of MIPS
Implementation
• Branches require the use of the ALU output to determine the next
instruction address, which comes either from the ALU (or from an
adder that increments the current PC by 4.

• Thick lines interconnecting the functional units represent buses,

which consist of multiple signals.

• Arrows are used to guide the reader in knowing how information

flows.
An Overview of MIPS
Implementation
• In practice, these data lines cannot simply be wired together; we must
add a logic element that choose from among the multiple sources

• This selection is commonly done with a device call a multiplexor, also

called data selector
An Overview of MIPS
Implementation
1

.
2

3
An Overview of MIPS
Implementation
• The multiplexor 1 controls what value replaces the PC
(PC + 4 or the branch destination address).

• The multiplexor is controlled by the gate that “ANDs” together the Zero output of the
ALU and a control signal that indicates that the instruction is a branch.

• Multiplexer 2 returns to the register file, is used to steer the output of the ALU (in the
case of an arithmetic-logical instruction) or the output of the data memory (in the case
of a load) for writing into the register file.

• Multiplexor 3 is used to determine whether the second ALU input is from the registers
(for an arithmetic-logical instruction or a branch) or from the offset field of the
instruction (for a load or store).
An Overview of MIPS
Implementation
• The added control lines are straightforward and determine:

 the operation performed at the ALU,

 whether the data memory should read or write, and
 whether the registers should perform a write operation.
MIPS Instruction Formats
• In MIS all instructions are of same length(32 bit).

• MIPS has 32 registers, numbered from 0 to 31, each with 32 bits. To identify
a register in MIPS we thus need 5 bits

• In order to represent different types of instructions 3 instruction formats

are used:
• I-format
• J-format, and
• R-format
I-format Instructions

• An I-Type instruction contains 4 fields:

• a 16 bit immediate field (immed. or address),
• two 5 bit register addresses (rt, rs) and
• 6 bit operation code (opcode)
I-format Instructions

• rs: source register (5 bits)

• rt: destination register (5 bits)

• 16-bit immediate value which may be used as an operand or an address.

• I- type /Immediate instructions, can be either Load/Store operations,

Branch operations, or Immediate ALU operations.
R-format instructions
• R-Type instructions, or Register instructions are used for register
based ALU operations.

• The two operands and the destination of the result are specified by
locations in the register file.
R-format instructions
• An R-Type instruction contains 6 fields:

• 6 bit opcode is the machinecode representation of the instruction mnemonic. Several

related instructions can have the same opcode.

• Shift (shamt) used with the shift and rotate instructions, specifies the amount by
which the source operand rs is rotated/shifted. This field is 5 bits long

• three 5 bit register addresses (rd, rt, rs), register source, register target and register
destination.

• Because several functions can have the same opcode, R-Type instructions need a
function (Func) code to identify what exactly is being done - for example, 0x00 refers
to an ALU operation and 0x20 refers to ADDing specifically. (6 bits)
J-Type instructions
• J instructions are used when a jump needs to be performed.

• The J instruction has the most space for an immediate value, because
addresses are large number

• A J-Type instruction contains 2 fields: a 26 bit jump destination

(target) and a 6 bit operation code (opcode).
Building a Datapath- Instruction Fetch
Components Involved
• Instruction memory: a memory unit to store instruction of a program and supply
instruction given an address.
• Program counter (PC): a register that hold the address of the current instruction.
• Adder: an adder to increment the PC to the address of the next instruction

A portion of the datapath used for fetching instructions and

incrementing
Building a Datapath- R-type
Instructions
• R-format instructions all read two registers, perform an ALU
operation on the contents of the register, and write the result to a
register.

• We call these instructions either R-type instructions or arithmetic-

logical instructions. This instruction class includes add, sub, AND, OR,
and slt.

• Eg: add $t1,$t2,$t3, ## $t1 = $t2 + $t3

Building a Datapath- R-type
Instructions
• The two elements needed to implement R-format ALU operations are
the register file and the ALU.
Building a Data path- R-type
Instructions
Register File:
• The processor’s 32 general-purpose registers are stored in a structure
called a register file.

• It has two read ports and one write port.

• For each data word to be read from the registers, we need an input to the
register fi le that specifies the register number to be read.

• The register file always outputs the contents of whatever register number
that are on the Read register inputs.
Building a Data path- R-type
Instructions
• To write a data word, we will need two inputs: one to specify the
register number to be written and one to supply the data to be
written into the register.

• Writes are controlled by the write control signal (RegWrite).

• Register number inputs are 5 bits wide to specify one of 32 registers

(32 = 25), whereas the data input and two data output buses are each
32 bits wide.
Building a Data path- R-type
Instructions
Component: ALU
• ALU, which takes two 32-bit inputs and produces a 32-bit result, and
well as a 1-bit signal Zero if the result is 0.

• The operation to be performed by the ALU is controlled with the ALU

operation signal, which will be 4 bits wide.

• Zero detection output of the ALU is used to implement branches

Building a Data path- Load/Store
Instructions
• load word (lw) and store word (sw) instructions, have the general
form:

Eg: lw $t1, offset ($t2) # $t1 = Memory [$t2 + offset]

sw $t1, offset ($t2) # Memory [$t2 + offset] = $t1

• These instructions compute a memory address by adding the base

register to the 16-bit signed off set field contained in the instruction.
Building a Data path- Load/Store
Instructions
• store instruction: the value to be stored must also be read from the
register file where it resides in $t1.

• Load instruction: the value read from memory must be written into the
register file in the specified register, which is $t1.

• So we will need both the register fi le and the ALU.

• The two units needed to implement loads and stores, in addition to the
register file and ALU, are the data memory unit and the sign extension unit
Building a Data path- Load/Store
Instructions
Building a Data path-
Load/Store Instructions
• The memory unit is a state element with inputs for the address and the
write data, and a single output for the read result.

• There are separate read and write controls.

• To add the 16 bit immediate field to a 32-bit register, the computer must
convert that 16- bit number to its 32-bit equivalent.(Memory [$t2 + offset] )

• sign extension unit is used to sign-extend the 16-bit off set field in the
instruction to a 32-bit signed value.
Building a Data path-
Load/Store Instructions
• The memory unit is a state element with inputs for the address and the
write data, and a single output for the read result.

• There are separate read and write controls.

• To add the 16 bit immediate field to a 32-bit register, the computer must
convert that 16- bit number to its 32-bit equivalent.(Memory [$t2 + offset] )

• Sign extension unit is used to sign-extend the 16-bit off set field in the
instruction to a 32-bit signed value.
Building a Data path- Branch-on-
Equal Instruction
• The beq branch instruction has three operands:

• two register that are compared for equality .

• 16-bit offset used to compute the branch target address relative to the branch
instruction address.

• Compute branch target address by adding the sign-extended off set fi eld of the
instruction to the PC

• Eg: beq $t1, $t2, offset # if ($t1 == $t2) go to (PC + 4) + (offset * 4)

Building a Data path- Branch-on-
Equal Instruction
• The data path for a branch uses the ALU to evaluate the branch
condition

• A separate adder is used to compute the branch target as the sum of

the incremented PC and the sign-extended, lower 16 bits of the
instruction shifted left 2 bits.

• The unit labeled Shift left 2 is simply a routing of the signals between
input and output that adds 00 two to the low-order end of the sign-
extended offset field
Building a Data path- Branch-on-
Equal Instruction
• Control logic is used to decide whether the incremented PC or branch
target should replace the PC, based on the Zero output of the ALU
Creating a Single Data path
Creating a Single Data path
• The simple data path for the core MIPS architecture combines the
elements required by different instruction classes.

• This data path can execute the basic instructions (load-store word,
ALU operations, and branches