Static & Dynamic RAM

Introduction
 The memory constructed with the help of transistors is known as
semiconductor memory.

 The semiconductor memories are termed as Random Access Memory(RAM),

because it is possible to access any memory location in random

 Depending on the technology used to construct a RAM, there are two types of
RAM :
 SRAM: Static Random Access Memory.
 DRAM: Dynamic Random Access Memory
 STATIC Memories
 Memories that consist of circuits capable of retaining their state as
long as power is applied are known as static memories.
 STATIC Memories
 Two inverters are cross-connected to form a latch.

 The latch is connected to two bit lines by transistors T1 and T2.

 These transistors act as switches that can be opened or closed under

control of the word line.

 When the word line is at ground level, the transistors are turned off
and the latch retains its state

 In order to read the state of the SRAM cell, the word line is activated to
close switches T1 and T2
 STATIC Memories
 If the cell is in state 1, the signal on bit line b is high and the signal on bit
line b’ is low. The opposite is true if the cell is in state 0.

 The Sense/Write circuit at the end of the two bit lines monitors their state
and sets the corresponding output accordingly.

 During a Write operation, the Sense/Write circuit drives bit lines b and b’
instead of sensing their state.

 It places the appropriate value on bit line b and its complement on b’ and
activates the word line.

 This forces the cell into the corresponding state, which the cell retains
when the word line is deactivated
 Static RAMs
 Continuous power is needed for the cell to retain its state.

 If power is interrupted, the cell’s contents are lost.

 When power is restored, the latch settles into a stable state, but not
necessarily the same state the cell was in before the interruption.

 SRAMs are said to be volatile memories because their contents are lost
when power is interrupted.

 Static RAMs can be accessed very quickly. Access times on the order of
a few nanoseconds are found in commercially available chips.
 Dynamic RAMs
 Static RAMs are fast, but their cells require several transistors.

 Less expensive and higher density RAMs can be implemented with

simpler cells.

 But, these simpler cells do not retain their state for a long period,
unless they are accessed frequently for Read or Write operations.

 Memories that use such cells are called dynamic RAMs (DRAMs).
 Dynamic RAMs
 Information is stored in a dynamic memory cell in the form of a charge
on a capacitor, but this charge can be maintained for only tens of
milliseconds.

 Since the cell is required to store information for a much longer time,
its contents must be periodically refreshed by restoring the capacitor
charge to its full value.

 A dynamic memory cell that consists of a capacitor, C, and a transistor,

T, is shown
Dynamic RAMs
 Dynamic RAMs
 To store information in this cell, transistor T is turned on and an appropriate
voltage is applied to the bit line. This causes a known amount of charge to be
stored in the capacitor.

 After the transistor is turned off, the charge remains stored in the capacitor,
but not for long. The capacitor begins to discharge.

 The information stored in the cell can be retrieved correctly only if it is read
before the charge in the capacitor drops below some threshold value.

 During a Read operation, the transistor in a selected cell is turned on.

 A sense amplifier connected to the bit line detects whether the charge stored
in the capacitor is above or below the threshold value
 Dynamic RAMs
 If the charge is above the threshold, the sense amplifier drives the bit
line to the full voltage representing the logic value 1.

 This voltage recharges the capacitor to the full charge corresponding

to the logic value 1.

 If the sense amplifier detects that the charge in the capacitor is below
the threshold value, it pulls the bit line to ground level ensuring
capacitor has no charge- representing logic value 0

 Since the word line is common to all cells in a row, all cells in a
selected row are read and refreshed at the same time.
Dynamic RAMs
15x215
decoder

15 bit row
address
215x211x23

11 x211 decoder
11 bit column
address
 Dynamic RAMs
 A 256-Megabit DRAM chip, configured as 32M × 8, is given.

 The cells are organized in the form of a 16K × 16K array.(214 rows and 214
columns

 The 16,384 cells in each row are divided into 2,048 groups of 8, forming 2,048
bytes of data.

 Therefore, 14 address bits are needed to select a row, and another 11 bits are
needed to specify a group of 8 bits in the selected row.

 In total, a 25-bit address is needed to access a byte in this memory.

 The high-order 14 bits and the low-order 11 bits of the address constitute the
row and column addresses of a byte, respectively.
 Dynamic RAMs
 During a Read or a Write operation, the row address is applied first. (A24-11)

 It is loaded into the row address latch in response to a signal pulse on an

input control line called the Row Address Strobe (RAS).

 This address is now fed to the row decoder, because there are number of
rows and we need to select one particular row from set of these rows

 This causes a Read operation to be initiated, in which all cells in the

selected row are read and refreshed.
 Dynamic RAMs
 Shortly after the row address is loaded, the column address( A10-0) is
applied to the address pins and loaded into the column address latch
under control of a second control line called the Column Address
Strobe.

 The information in this latch is decoded and the appropriate group of 8

Sense/Write circuits is selected.
 Dynamic RAMs
 If the R/W control signal indicates a Read operation, the output values
of the selected circuits are transferred to the data lines, D7−0.

 For a Write operation, the information on the D7−0 lines is transferred

to the selected circuits, then used to overwrite the contents of the
selected cells in the corresponding 8 columns.

 The timing of the operation of the DRAM is controlled by the RAS and
CAS signals.

 These signals are generated by a memory controller circuit external to

the chip when the processor issues a Read or a Write command.

 Such memories are referred to as asynchronous DRAMs

 Dynamic RAMs
 It is important to note that the application of a row address causes all the
cells on the corresponding row to be read and refreshed during both Read
and Write operations.

 To ensure that the contents of a dynamic memory are maintained, each

row of cells must be addressed periodically, typically once every two
milliseconds.

 Another feature available on many dynamic memory chips is that once the
row address is loaded, successive locations can be accessed by loading
only column addresses.(fast page mode)

 Because of their high density and low cost, dynamic memories are widely
used in the main memory units of computers.
 SRAM vs.DRAM

 Both static and dynamic RAMs are volatile, that is, it will
retain the information as long as power supply is applied.

 A dynamic memory cell is simpler and smaller than a static

memory cell. Thus a DRAM is more dense, i.e., packing
density is high (more cell per unit area).

 DRAM is less expensive than corresponding SRAM.

 SRAM vs.DRAM

 DRAM requires the supporting refresh circuitry. For larger

memories, the fixed cost of the refresh circuitry is more
than compensated for by the less cost of DRAM cells.

 SRAM cells are generally faster than the DRAM cells.

Therefore, to construct faster memory modules (like cache
memory) SRAM is used.

 In static Ram we are using a latch to store single bit where

as in dynamic RAM we are making use of a capacitor
 Synchronous DRAM
 In the early 1990s, developments in memory technology resulted in
DRAMs whose operation is synchronized with a clock signal

 Such memories are known as synchronous DRAMs (SDRAMs)

 The cell array is the same as in asynchronous DRAMs.

 The distinguishing feature of an SDRAM is the use of a clock signal, the

availability of which makes it possible to incorporate control circuitry
on the chip.
Synchronous DRAM
 Synchronous DRAM
 Here also row and column address can be provided.

 once we apply a row address, that particular address go to row

decoder.

 Instead of column address latch there is a counter that will be used to

count to the next, next column for faster access.

 The output of individual sense/write circuit is connected to a latch

 And the sense/write circuits and these latches are connected to the
data input register and data output register.
 Synchronous DRAM
 Data input register will be required when we have to transfer a data
from a data bus to this particular cell.

 And if you want to output something from this chip it will be

transferred to data output register.

 We have a mode register to select different modes of operation and a

timing control register associated with clock.

 There is an inbuilt refresh counter that refreshes the rows of these

cells periodically.
 Synchronous DRAM
 For READ operation the row address is applied first.

 In response to the column address the data present in the latches of the
selected columns are transferred to the data output registers.

 From the data output registers the data is then available in the data bus
and finally reaches the processor.

 Similarly, for WRITE operation the row address is applied first.

 In response to the column address, the data present in the data bus is
made available to the latches through the data input register.
 Synchronous DRAM
 And then finally, the data is written to the particular cell.

 Synchronous DRAMs can deliver data at a very high rate.

 New data are placed on the data lines at the rising edge of each clock
pulse.
 Structure of Larger Memories
 We have discussed the basic organization of memory circuits as they may
be implemented on a single chip.

 How memory chips may be connected to form a much larger memory.

 Consider a memory consisting of 2M words of 32 bits each(or 64Mbit

Memory).

 We will see how this memory can be implemented using 512K × 8 static
memory chips.

 First we need to identify how many chips are needed.

 So we need 4x4 =16 512K X 8 chips to implement such a memory
 Structure of Larger Memories
 These chips can be organized as 4 rows and 4 columns.

 Since the chip is 512k x 8 each chip contains 2 19 rows and 23=8 columns.

 We need to access 32 bit word at a time.

 So retrieving one row of chips will do our purpose.

 From 4 rows(of chip) to uniquely identify 1 row we need 2 bits

 This will select a row of 4 chips.

 From each chip we are retrieving 8 bits.(512k x 8 chip)

Structure of Larger Memories
 Structure of Larger Memories
 Retrieving 8 bits each from 4 chips in a row will give 32 bits.
 So to retrieve 8 bits from a chip we need to select 1 row from chip out of
219 rows.
 This requires 219 bits.
 So in this arrangement we need to use 21-bit addressing.
 2 bits for identifying one particular row of chips and 19 –bit address for
identifying one row in each chip
 Structure of Larger Memories
 Each chip has a control input called Chip-select.

 When this input is set to 1, it enables the chip to accept data from or to place data on its
data lines.

 Only the selected chip places data on the data output line, while all other outputs are
electrically disconnected from the data lines.

 Twenty-one address bits are needed to select a 32-bit word in this memory.

 The high-order two bits of the address are decoded to determine which of the four rows
should be selected.

 The remaining 19 address bits are used to access specific byte locations inside each chip
in the selected row.
 The R/W inputs of all chips are tied together to provide a common Read/Write control line
Example 2:
Construct a 4M X 16 memory module using 256K X 4 memory chips

So we need 64 256K x 4 chips to implement this memory circuit with 16

rows and 4 columns
Structure of Larger Memories

 Since the circuit has 16 rows 4 bits are needed to select a row of chips.

 From within a chip we need to select 4 bits.

 In order to select one row from a 256K x 4 chip we need 18

bits(256K=218)

 So 22 bits are needed to select 16 bit word in this memory.

 4x 16 decoder used to select row of chips and 18-bits to select a row

within the chip
READ ONLY MEMORY
Read-only Memories
 Both static and dynamic RAM chips are volatile, which means that they retain
information only while power is turned on.

 But there are many applications requiring memory devices that retain the stored
information when power is turned off.

 Eg: storing bootstrap loader which loads OS when computer is turned on.

 We need to store the instructions into a non-volatile memory .

 Non-volatile memory is read in the same manner as volatile memory.

 Separate writing process is needed to place information in this memory

 Read-only Memories
 Since its normal operation involves only reading the stored data, a memory of this type is
called a read-only memory (ROM).

 information can be written into it only once at the time of manufacture.

Programmable ROM (PROM)

 Allow the data to be loaded by the user.

 Process of inserting the data is irreversible.

 PROMs provide flexibility and convenience not available with ROMs

 Storing information specific to a user in a ROM is expensive.

 Read-only Memories
EPROM—Erasable Programmable ROM

 Allows the stored data to be erased and new data to be written into it.

 Flexibility, useful during the development phase of digital systems as memory

changes and updates can be easily made.

 Exposing the chip to ultraviolet light erases the entire contents of the chip.
Read-only Memories
Electrically Erasable Programmable Read-Only Memory
(EEPROM)

 An EPROM must be physically removed from the circuit for reprogramming

 The entire contents of the chip are erased when exposed to ultraviolet light

 EEPROM is another type of erasable PROM that can be programmed, erased,

and reprogrammed electrically.

 It does not have to be removed for erasure, and it is possible to erase the cell
contents selectively.

 different voltages are needed for erasing, writing, and reading the stored
 Read-only Memories
Flash Memory
 Uses an approach similar to EEPROM technology.

 It is possible to read the contents of a single cell

 It is only possible to write an entire block of cells and prior to

writing, the previous contents of the block are erased.

 Flash devices have greater density, which leads to higher

capacity and a lower cost per bit.
 Read-only Memories
Flash Memory
 They require a single power supply voltage, and consume less power
in their operation.

 The low power consumption of flash memories makes them attractive

for use in portable, battery-powered equipment.

 Eg: hand-held computers, cell phones, digital cameras etc.

 Single flash chips are not sufficiently large, so larger memory

modules consisting of no: of chips are implemented using flash cards
and flash drives.
 Read-only Memories
Flash Cards
 One way of constructing large module is to mount flash chips on
a small card.

 Cards can be plugged into a convenient accessible slot.

 Flash cards come in variety of sizes

 Capacity ranges from 512MB to 16GB

 Read-only Memories
Flash Drives
 Larger Flash memory modules have been developed to replace hard disk
drives.

 They have shorter seek and access time, resulting in faster response.
 They have lower power consumption, making them suitable for battery
driven applications.

 Disadvantage is smaller capacity and high cost per bit when compared to
hard drives

 Another disadvantage is flash memory deteriorate after it has been written

a no:of times
 Speed, Size, and Cost
 A big challenge in the design of a computer system is to provide a sufficiently
large memory, with a reasonable speed at an affordable cost.
Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a complex circuit
making it impossible to pack a large number of cells onto a single chip.
Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive, but significantly
slower than SRAMs.
Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary.
 Secondary storage such as magnetic disks provide a large amount of storage,
but is much slower than DRAMs
Speed, Size, and Cost
 Speed, Size, and Cost
 Fastest access is to the data held in processor registers. Registers are at
the top of the memory hierarchy.
 Relatively small amount of memory that can be implemented on the
processor chip called processor cache.
 Two levels of cache. Level 1 (L1) cache is on the processor chip.
 Level 2 (L2) cache is in between main memory and processor,
implemented using SRAM chip.
 Next level is main memory, implemented as SIMMs.(simple in-line memory
module) Much larger, but much slower than cache memory.
 Next level is magnetic disks which provides huge amount of inexpensive
storage.
 The idea is to bring instructions and data that will be used in the near future
as close to the processor as possible.