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Memory

The document discusses the basic concepts of memory organization, including addressing schemes, memory types (RAM and ROM), and data transfer between the CPU and memory. It explains how memory is structured in arrays, the role of registers like MAR and MDR, and the operations for reading and writing data. Additionally, it covers the internal organization of memory chips, highlighting different configurations and the necessary connections for data and control lines.

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4 views21 pages

Memory

The document discusses the basic concepts of memory organization, including addressing schemes, memory types (RAM and ROM), and data transfer between the CPU and memory. It explains how memory is structured in arrays, the role of registers like MAR and MDR, and the operations for reading and writing data. Additionally, it covers the internal organization of memory chips, highlighting different configurations and the necessary connections for data and control lines.

Uploaded by

Haf hafeefa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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MODULE 5

The memory system – basic concepts, semiconductor RAM memories,


Static and dynamic RAM, Structure of larger memories, semiconductor
ROM memories, Speed, size and cost
Memory Organization-Basics
• The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.

• In modern computers individual address is assigned for each byte of


information, and it is called byte-addressable computer

• The memory is usually designed to store and retrieve data in word-length


quantities.

• Word length: no: of bits stored or retrieved in one memory access.

• A byte addressable 32-bit computer, each memory word contains 4 bytes


Memory Organization-Basics
• A computer with memory of 64KB =216 Bytes. We need 16
bit address to uniquely identify each memory location

• Machines with 32-bit addresses can utilize a memory that


contains up to 232 locations.

• The number of locations represents the size of the address


space of the computer.
Memory Organization-Basics
• Consider a machine with 32 bit address bus.

• If the word size is 32 bit, then the high order 30 bit will specify the
address of a word.

• If we want to access any byte of the word, then it can be specified


by the lower two bit of the address bus
Memory Organization-Basics
Memory Organization-Basics
• The data transfer between main memory and the CPU
takes place through two CPU registers.
• MAR : Memory Address Register and
• MDR : Memory Data Register.

• If the MAR is k-bits, then the total addressable memory


location will be 2k.

• If the MDR is n-bits, then the n bit of data is transferred in


one memory cycle
Memory Organization-Basics

• This transfer takes place through processor bus which has


k address lines and n data lines.

• The bus also has control lines like Read/Write and


Memory Function Complete (MFC) for coordinating data
transfer.

• CPU initiates a memory operation by loading the


appropriate data i.e., address to MAR.
Memory Organization-Basics
Memory read operation:

• Loads address of required memory location into MAR register.

• Sets the R/W line to 1.

• Then the contents of the memory location is brought to MDR.

• The memory control circuitry indicates this to the CPU by setting


MFC to 1
Memory Organization-Basics
Memory write operation :
• CPU loads the data into MDR .

• It loads address of the memory location in MAR.

• Sets the R/W line to 0.

• Once the contents of MDR are stored in specified


memory location, then the memory control circuitry
indicates the end of operation by setting MFC to 1.
Memory Organization-Basics
Measures for the speed of a memory:
Memory access time: time that elapses between the initiation of an
operation to transfer a word of data and the completion of that
operation.

Memory cycle time: the minimum time delay required between the
initiation of two successive memory operations, for example, the time
between two successive Read operations.

A memory unit is called a random-access memory (RAM) if the access


time to any location is the same, independent of the location’s
address
INTERNAL ORGANIZATION
OF MEM.CHIPS
Internal organization of memory chips
• Memory cells are organized in the form of an array and each
memory cell can hold one bit of information.

• One row is one memory word and all cells of a row are connected
to a common line, known as the “word line’.

• Word line is connected to the address decoder.

• At a particular instant one word line is enabled depending on the


address present in the address bus.
Internal organization of memory chips
Internal organization of memory chips

• The cells in each column are connected by two lines known as bit
lines.

• These lines are connected to data input and data output line through
a sense/write circuit

• During a Read operation, these circuits sense, or read, the


information stored in the cells selected by a word line and place this
information on the output data lines.

• During a Write operation, the Sense/Write circuits receive input data


and store them in the cells of the selected word.
Internal organization of memory chips

• Above memory chip consists of 16 words of 8 bits each. This is


referred to as a 16 × 8 organization

• The data input and the data output of each Sense/Write circuit are
connected to a single bidirectional data line that can be connected
to the data lines of a computer.

• For 16 words we need an address bus of 4 lines.

• Two control lines, R/W and CS, are provided.


Internal organization of memory chips
• The R/W (Read/Write) input specifies the required operation

• The CS (Chip Select) input selects a given chip in a multichip


memory system

• The circuit needs 14 external connections for address, data, and


control lines.

• It also needs two lines for power supply and ground connection
Internal organization of memory chips
• Consider now a slightly larger memory circuit, one that has 1K
(1024) memory cells.

• This circuit can be organized as a 128 × 8 memory, with 128 words


of size 8 bits.

• So size of data bus is 8 bits, and size of address bus is 7 bits


(27=128), 2 control lines and 2 lines for power supply, requiring a
total of 19 external connections.
Internal organization of memory chips
Internal organization of memory chips
• The same number of cells can be organized into a 1K×1 format,
with 1024 words each of 1 bit.

• So size of data bus is 1 and address bus is 10.

• Several memory words are arranged in a row.

• Here address bus is divided into two groups: one for row address
and other for column address

• The 10-bit address is divided into two 5 bit groups, each to form
the row and column address of the cell array.
Internal organization of memory chips
• A row address selects a row of 32 cells, all of which are accessed
in parallel.

• But, only one of these cells is connected to the external data line
via input output multiplexer , based on the column address
Internal organization of memory chips

• Commercially available chips contains much larger memory cells.

• Large chips have the same organization of the examples discussed.

• But they hare larger no: of memory cells & external connections.

• For example a 4M-bit chip may have a 512K X 8 organization in


which case 19 addresses and 8 data input/output pins are needed

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