Computer Organization and Architecture

UNIT-1
Register Transfer and Micro-Operations: Register Transfer Language, Register Transfer,
memory Transfers, Bus construction with Multiplexers, Arithmetic Micro-operations, Logic
Micro-operations, Shift Micro-operations, Arithmetic Logic Shift Unit.
UNIT-2
Basic Computer Organization: Instruction codes, Computer Registers, Computer Instructions,
Timing and Control, Instruction Cycle, Memory-Reference Instructions, Input- Output and
Interrupt.
UNIT-3
Central Processing Unit: General registers Organization, Stack Organization, Instruction
Formats, Addressing Modes, Data Transfer and Manipulation, Program Control
UNIT-4
Computer Arithmetic: Introduction, Addition and Subtraction, Booth Multiplication Algorithm.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory, Associative
Memory, Cache Memory, Virtual Memory.

UNIT-5
Input-Output Organization: Peripheral Devices, Input-output Interface, Asynchronous Data
Transfer, Priority Interrupt, Direct Memory Access (DMA), Input-Output Processor.
Pipeline and Parallel Processing: Parallel processing, Pipelining, Arithmetic pipeline,
Instruction pipeline.
 Course Outcomes
CO1: Understand the basic functional units of a
computer system and its organization (L2)
CO2: Apply appropriate instructions for processing
various types of computer operations (L3).
CO3: Apply various types of organizations on
registers (L3).
CO4: Analyze memory hierarchy, I/O
communication and pipelining (L4).

L1-remembering, L2-understanding, L3-applying, L4-analyzing, L5-evaluating, and L6-creating.

 UNIT-4
Computer Arithmetic: Introduction, Addition and Subtraction, Booth
Multiplication Algorithm.

Memory Organization: Memory Hierarchy, Main Memory, Auxiliary

memory, Associative Memory, Cache Memory, Virtual Memory.

3
 Unit-4-Part-1
Computer Arithmetic
 Addition and Subtraction
 Multiplication Algorithms
•
Introduction
Arithmetic instructions in digital computer manipulate data to produce re­sults necessary
for the solution of computational problems.
• The four basic arithmetic operations are addition, subtraction, multiplication and division.
• An arithmetic processor is the part of a processor unit that executes arithmetic
operations.
• The data type assumed to reside in processor registers during the execution of an
arithmetic instruction is specified in the definition of the instruction.
• An arithmetic instruction may specify binary or decimal data, and in each case the data
may be in fixed point or floating-point form.
• Fixed-point numbers may represent integers or fractions.
• Negative numbers may be in signed-magnitude or signed complement representation.
• We consider addition, subtraction, multiplication, and division for the following types of
data:
1. Fixed-point binary data in signed-magnitude representation
2. Fixed-point binary data in signed-2's complement representation
3. Floating-point binary data
Complements are used in digital computers for
4. Binary-coded decimal (BCD) data simplifying the subtraction operation and for
logical manipulation
 Complements 6 / 23

 Subtraction of Unsigned Numbers (M-N), N0

 1) M + (rn-N)
 2) M  N : Discard end carry, Result = M-N
 3) M  N : No end carry, Result = - r’s complement of (N-M)

» Decimal Example)
M  N 72532(M) - 13250(N) = 59282 MN 13250(M) - 72532(N) = -59282
72532 13250
+ 86750 (10’s complement of 13250) + 27468 (10’s complement of 72532)
Discard
End Carry 1 59282 0 40718
No End Carry
Result = 59282 Result = -(10’s complement of 40718)
= -(59281+1) = -59282
» Binary Example)
X  Y 1010100(X) - 1000011(Y) = 0010001 XY 1000011(X) - 1010100(Y) = -0010001
1010100 1000011
+ 0111101 (2’s complement of 1000011) + 0101100 (2’s complement of 1010100)
1 0010001 0 1101111
Result = 0010001 Result = -(2’s complement of 1101111)
= -(0010000+1) = -0010001

Unit-1 Data Representation

 3. Fixed-Point Representation 7 / 23
*Numeric Data
1) Fixed Point
 Fixed-Point Representation 2) Floating Point
 Computers must represent everything with 1’s and 0’s, including the
sign of a number and fixed/floating point number
* 32.25
 Binary/Decimal Point 1) 0.25, 2) 32.0, 3) 32.25
 The position of the binary/decimal point is needed to represent fractions,
integers, or mixed integer-fraction number
 Two ways of specifying the position of the binary point in a register
 1) Fixed Point : the binary point is always fixed in one position
» A binary point in the extreme left of the register(Fraction : 0.xxxxx)
» A binary point in the extreme right of the register(Integer : xxxxx.0)
 The binary point is not actually present, but the number stored in the register is treated
as a fraction or as an integer
 2) Floating Point : the second register is used to designate the position of the
binary point in the first register
* MSB for Sign
 Integer Representation +14 -14 “0” is plus +
 Signed-magnitude representation “1” is minus -
0 0001110 1 0001110
Most  Signed-1’s complement representation
Common 0 0001110 1 1110001
 Signed-2’s complement representation
0 0001110 1 1110010

Unit-1 Data Representation

 3. Fixed-Point Representation 8 / 23

 Arithmetic Addition (-12) + (-13) = -25

 Addition Rules of Ordinary Arithmetic (+12) + (+13) = +25
» The signs are same : sign= common sign, result= add (+25) + (-37)
» The signs are different : sign= larger sign, result= larger-smaller = 37 - 25 = -12
 Addition Rules of the signed 2’s complement *Addition Exam)
» Add the two numbers including their sign bits + 6 00000110 - 6 11111010
» Discard any carry out of the sign bit position + 13 00001101 + 13 00001101
 Arithmetic Subtraction + 19 00010011 + 7 00000111

 Subtraction is changed to an Addition + 6 00000110 - 6 11111010

» (± A) - (+ B) = (± A) + (- B) - 13 11110011 - 13 11110011
- 7 11111001 - 19 11101101
» (± A) - ( - B) = (± A) + (+ B)

* Subtraction Exam) (- 6) - ( - 13) = +7

11111010 - 11110011 = 11111010 + 2’s comp of 11110011
Discard = 11111010 + 00001101
End Carry = 1 00000111 = +7
 Overflow
 Two numbers of n digits each are added and the sum occupies n+1 digits
 n + 1 bit cannot be accommodated in a register with a standard length of n
bits(many computer detect the occurrence of an overflow, and a
corresponding F/F is set)

Unit-1 Data Representation

 Addition and Subtraction

Addition and Subtraction with Signed-Magnitude Data

Hardware Algorithm
 Addition and Subtraction with Signed-2's
• + 33 is represented as 00100001 and - 33 as 1101 1 1 1 1 .
• Note that 11011111 is the 2's complement of 00100001, and vice versa.
• The addition of two numbers in signed-2's complement form consists of adding the numbers
with the sign bits treated the same as the other bits of the number.
• A carry-out of the sign-bit position is discarded.
• The subtraction consists of first taking the 2' s complement of the subtrahend and then adding it
to the minuend.
 Multiplication Algorithms
• Multiplication of two fixed-point binary numbers in signed-magnitude representation
• The process consists of looking at successive bits of the multiplier, least significant bit
first.
• If the multiplier bit is a 1, the multiplicand is copied down; otherwise, zeros are copied
down.
• The numbers copied down in successive lines are shifted one position to the left from
the previous number.
• Finally, the numbers are added and their sum forms the product.
 Hardware Implementation for Signed-Magnitude Data

• When multiplication is implemented in a digital computer, it

is convenient to change the process slightly.
• First, instead of providing registers to store and add
simultaneously as many binary numbers as there are bits in
the multiplier, it is convenient to provide an adder for the
summation of only two binary numbers and successively
accumulate the partial products in a register.
• Second, instead of shifting the multiplicand to the left, the
partial product is shifted to the right, which results in
leaving the partial product and the multiplicand in the
required relative positions.
• Third, when the corresponding bit of the multiplier is 0,
there is no need to add all zeros to the partial product since
it will not alter its value.
 Hardware Implementation for Signed-Magnitude Data
• Initially, the multiplicand is in
register B and the multiplier in Q.
• The sum of A and B forms a partial
product which is transferred to the Multiplicand Number of bits in the multiplier
EA register.
• Both partial product and multiplier
are shifted to the right.
• This shift will be denoted by the
statement shr EAQ to designate
the right shift depicted in Fig. 10-5.
• The least significant bit of A is
shifted into the most significant
position of Q, the bit from E is multiplier
shifted into the most significant
position of A, and 0 is shifted into
E.
• After the shift, one bit of the
partial product is shifted into Q,
pushing the multiplier bits one
position to the right. partial product
• In this manner, the rightmost flip-
flop in register Q, designated by
Qn, will hold the bit of the
multiplier, which must be
inspected next.
Hardware Algorithm
• Initially, the multiplicand is in B and the multiplier in Q.
• Their corresponding signs are in Bs, and Qs., respectively.
• The signs are compared, and both A and Q are set to correspond to
the sign of the product since a double-length product will be stored
in registers A and Q.
• Registers A and E are cleared and the sequence counter SC is set to a
number equal to the number of bits of the multiplier.
• We are assuming here that operands are transferred to registers from
a memory unit that has words of n bits.
• Since an operand must be stored with its sign, one bit of the word
will be occupied by the sign and the magnitude will consist of n - 1
bits.
• After the initialization, the low-order bit of the multiplier in Q, is
tested.
• If it is a 1, the multiplicand in B is added to the present partial
product in A .
• If it is a 0 , nothing is done. Register EAQ i s then shifted once to
the right to form the new partial product.
• The sequence counter is decremented by 1 and its new value
checked.
• If it is not equal to zero, the process is repeated and a new
partial product is formed.
• The process stops when SC = 0.
• Note that the partial product formed in A is shifted into Q one
bit at a time and eventually replaces the multiplier.
• The final product is available in both A and Q, with A holding the
most significant bits and Q holding the least significant bits.
 Booth Multiplication Algorithm
• Booth algorithm gives a procedure for multiplying binary integers in signed-2's complement
representation.
• It operates on the fact that strings of 0's in the multiplier require no addition but just shifting, and
a string of 1's in the multiplier from bit weight 2 k to weight 2m can be treated as 2K+1 - 2m.

• For example, the binary number 001 110 ( + 14) has a string of 1's from 2 3 to 21. (k = 3, m = 1).
• The number can be represented as 2k+ l - 2m = 24 - 21 = 16 - 2 = 14.

• Therefore, the multiplication M x 14, where M is the multiplicand and 14 the multiplier, can be
done as M x 24 - M X 21

• Thus the product can be obtained by shifting the binary multiplicand M four times to the left and
subtracting M shifted left once.

• Booth algorithm requires examination of the multiplier bits and shifting of the partial product.
Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the
partial product, or left unchanged according to the following rules:

1. The multiplicand is subtracted from the partial product upon encountering the first least
significant 1 in a string of 1's in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0 (provided that
there was a previous 1) in a string of 0's in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the previous
multiplier bit.
Hardware for Booth algorithm.
Flowchart for Booth algorithm
(-9)*(-13)=+117
 Example : (-5)*(-7)=+35
BR = -5 = 1011, BR'+1 = 0101
QR = -7 = 1001

OPERATION AC QR Qn+1 SC
0000 1001 0 4
AC + BR’ + 1 0101 1001 0
ASHR 0010 1100 1 3
AC + QR 1101 1100 1
ASHR 1110 1110 0 2
ASHR 1111 0111 0 1
AC + BR’ + 1 0010 0011 1 0

Product is calculated as follows:

Product = AC QR Product = 0010 0011 =
35
 Array Multiplier; Fast approach
 Checking the bits of the multiplier one at a time and forming partial products is a
sequential operation that requires a sequence of add and shift microoperations.
 The multiplication of two binary numbers can be done with one microoperation by
means of a combinational circuit that forms the product bits all at once.
 This is a fast way of multiplying two numbers since all it takes is the time for the signals
to propagate through the gates that form the multiplication array.
 However, an array multiplier requires a large number of gates, and for this reason it was
not economical until the development of integrated circuits.
Array Multiplier; Fast approach
4 bit by 3 bit array muhiplier.