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Topic5 Mux

The document explains the concept of a multiplexer (MUX), which selects one of several input bits to output based on addressing bits. It details the structure of a 4-to-1 multiplexer, the differences between multiplexers and decoders, and provides examples of constructing larger multiplexers using smaller ones. Additionally, it introduces a quadruple 2-to-1 line multiplexer for outputting multiple bits.

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4 views13 pages

Topic5 Mux

The document explains the concept of a multiplexer (MUX), which selects one of several input bits to output based on addressing bits. It details the structure of a 4-to-1 multiplexer, the differences between multiplexers and decoders, and provides examples of constructing larger multiplexers using smaller ones. Additionally, it introduces a quadruple 2-to-1 line multiplexer for outputting multiple bits.

Uploaded by

coolguysa123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Chapter2 Digital

Components
Multiplexer (MUX)

A multiplexer can use addressing bits to


select one of several input bits to be the
output.

 A selector chooses a single data input


and passes it to the MUX output
 It has one output selected at a time.
4 to 1 line multiplexer

4 to 1 line
multiplexer
S1 S0 F
2n MUX to 1
0 0 I0
n for this MUX is 2 0 1 I1

This means 2 1 0 I2

selection lines s0 1 1 I3

and s1
Multiplexer (MUX)
 Consists of:

Inputs (multiple) = 2n

Output (single)

Selectors (# depends on # of inputs) = n

Enable (active high or active low)
Function table with
enable
Multiplexers versus
decoders
• A Multiplexer uses n binary select bits to choose
from a maximum of 2n unique input lines.
•Multiplexers and decoders both can decode
minterms.
•Decoders have n number of output lines while
multiplexers have only one output line.
•The decoded minterms are used to select data from
one of up to 2n unique data input lines.
•The output of the multiplexer is the data input
whose index is specified by the n bit code.
Multiplexer Versus
I3
Decoder

I2

I1

I0
S1

S0

2-t0-4 Decoder
4-to-1 Multiplexer
Note that the multiplexer has an extra OR gate. A1 and A0 are
the two inputs in decoder. There are four inputs in multiplexer.
Function table with
enable
Cascading multiplexers

Using three 2-1 MUX


to make one 4-1 MUX

S1 S0 F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Example: Construct an
8-to-1 multiplexer using I0
2-to-1 multiplexers. I1

S2 S1 S0 F I2
0 0 0 I0 I3
2-1 F
0 0 1 I1 MUX

S E
0 1 0 I2
I4 S2 E
0 1 1 I3
I5
1 0 0 I4
1 0 1 I5
1 1 0 I6 I6
1 1 1 I7 I7
Example ( ) Construct 8-to-1 multiplexer using one 2-to-1 multiplexer and
two 4-to-1 multiplexers

S2 S1 S0 X
Quadruple 2-to-1 Line Multiplexer

Used to supply four bits to the


output. In this case two inputs four
bits each.
Quadruple 2-to-1 Line
Multiplexer

E S Y
(Enable) (Select) (Output)
0 X All 0’s

1 0 A

1 1 B

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