Purpose of This Chapter:

In this chapter we introduce a basic computer and show how its operation can
be specified with register transfer statements.

The basic computer presented in this chapter is very small compared to

commercial computers,

It has the advantage of being simple enough so we can demonstrate the design
process without too many complications.
Instruction Codes
A process is controlled by a program
– A program is a set of instructions that specify
the operations, data, and the control sequence
– An instruction is stored in binary code that
specifies a sequence of microoperations
– Instruction codes together with data are stored
in memory (Stored Program Concept)
Direct address
Occurs When the Operand Part Contains the Address of
Needed Data.

1. Address part of IR is placed on the bus and loaded

back into the AR

2. Address is selected in memory and its Data placed on

the bus to be loaded into the Data Register to be used
for requested instructions
Direct address
Indirect address
Occurs When the Operand Contains the Address of the Address
of Needed Data.

1. Address part of IR is placed on the bus and loaded back

into the AR

2. Address is selected in memory and placed on the bus to

be loaded Back into the AR

3. New Address is selected in memory and placed on the bus

to be loaded into the DR to use later
Indirect address
Effective address:
• Effective address: Address where an
operand is physically located

Effective address: 457 Effective address: 1350

5-2 Computer Registers
•Computer instructions are normally stored in consecutive memory
locations and are executed sequentially one at a time.

•The control reads an instruction from a specific address in memory and

executes it. It then continues by reading the next instruction in sequence
and executes it, and so on. This type of instruction sequencing needs a
counter to calculate the address of the next instruction after execution of
the current instruction is completed.

•It is also necessary to provide a register in the control unit for storing the
instruction code after it is read from memory.

•The computer needs processor registers for manipulating data and a

register for holding a memory address.

•These requirements dictate the register configuration shown in Fig. 5-3.

The registers are also listed in Table 5-1 together with a brief description
of their function and the number of bits that they contain.
 The address register is connected to the memory
+1
The Program Counter points to PC
the next address of the program
000000000010
00000001

1. Program Counter Increments

by units of addresses AR 000000000010
2. The next address is put on
the bus and is loaded into the
Direct access to
Address Register
Memory
3. The Bits of the AR are wired
directly to the RAM Address
lines to enable loading the
memory into the Instruction R. IR 1010101010101010
Figure 5-4: Common Bus System s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
 Common Bus System
– The connection of the registers and memory of the
basic computer to a common bus system :

– The outputs of seven registers and memory are connected to the

common bus
– The specific output is selected by mux(S0, S1, S2) :
» Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)
» When LD(Load Input) is enable, the particular register
receives the data from the bus
– Control Input : LD, INC, CLR, Write, Read
 COMMON BUS SYSTEM

• Control variables: The bus is controlled by

• 1- Selection switches for selecting the

source of information and
• 2- Enable switches at the destination device
to accept the information.
 Selection variables

• Selection variables: select a register or the

memory whose output is used as an input to the
common bus.

• To select one device out of 8, we need 3 select

variables.
• For example, if S2S1S0 = 011, the output of DR is
selected as an output of the common bus.
 Load input

Load input (LD): Enables the input of a

register to download bits form the common
bus. When LD = 1 for a register, the data on
the common bus is read into the register
during the next clock pulse transition.
> Increment input (INR): Increments the content of a register.
> Clear input (CLR): Clear the content of a register to zero.
 Incompatibility in register sizes
• When the contents of AR or PC (12 bits) are
applied to the 16-bit common bus, the four most
significant bits are set to zero. When AR or PC
receives information from the bus, only the 12
least significant bits are transferred to the register.

12 least significant bits

12 bits
5.3 Computer Instructions
 5-3. Computer Instruction
•
– 3 Instruction Code Formats : Fig. 5-5 Hex Code
Symbol I =0 I =1 Description
• Memory-reference instruction AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
–Opcode = 000  110 LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
»I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BUN 4xxx Cxxx Branch unconditionally
I=0 : Direct, 15 14 12 11 0 BSA 5xxx Dxxx Branch and Save return address
I=1 : Indirect ISZ 6xxx Exxx Increment and skip if zero
I Opcode Address CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
»Register-reference instruction CME m 7100 e Comp
CIR 7080 Circulate right AC and E
–7xxx (7800 ~ 7001) : CLA, CMA, CIL 7040 Circulate left AC and E
15 14 12 11 0 INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
0 1 1 1 Register Operation
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
–Input-Output instruction SZE
HLT
7002
7001
Skip next instruction if E is 0
Halt computer
–Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, INP
OUT
F800
F400
Input character to AC
Output character from AC
SKI F200 Skip on input flag
15 14 12 11 0
SKO F100 Skip on output flag
1 1 1 1 I/O Operation ION F080 Interrup
IOF F040 Inter
5.4: Timing & Control:

 The timing for all registers in the basic computer is controlled

by a master clock generator.
 The clock pulses are applied to all flip-flops and registers in the
system, including the flip-flops and registers in the control unit.
 The clock pulses do not change the state of a register unless the
register is enabled by a control signal.
 The control signals are generated in the control unit and
provide control inputs for the multiplexers in the common bus,
control inputs in processor registers, and microoperations for the
accumulator.
 CONTROL UNIT HARDWARE (Hardwired)
• Inputs to the control unit come from IR where an instruction is stored.
• A hardwired control is implemented in the example computer using:
> A 3x8 decoder to decode opcode bits 12-14 into signals D0, ..., D7;

A flip-flop (I) to store the addressing mode bit in IR

5.5: Instruction Cycle:
A program residing in the memory unit of the computer consists
of a sequence of instructions. The program is executed in the
computer by going through a cycle for each instruction.
Each instruction cycle in turn is subdivided into a sequence of
sub-cycles or phases. In the basic computer each instruction cycle
consists of the following phases:
1.Fetch an instruction from memory.
2.Decode the instruction.
3.Read the effective address from memory if the instruction has
an indirect address.
4.Execute the instruction.
Fetch and Decode:
T0: AR  PC
T1: IR  M[AR], PC  PC + 1
T2: D0, • • • , D7 <- Decode IR(12-14), AR  IR(0-11),
1  IR(lS)