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ORCATOP

The document outlines the steps for performing sanity checks, floor planning, and macro placement in a design process. It emphasizes the importance of addressing errors related to port placement, power planning, and maintaining proper cell and pin density. Additionally, it details the procedures for checking and fixing errors during the CTS and routing stages to ensure a successful design implementation.

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mbalaji00000
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38 views23 pages

ORCATOP

The document outlines the steps for performing sanity checks, floor planning, and macro placement in a design process. It emphasizes the importance of addressing errors related to port placement, power planning, and maintaining proper cell and pin density. Additionally, it details the procedures for checking and fixing errors during the CTS and routing stages to ensure a successful design implementation.

Uploaded by

mbalaji00000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ORCATOP

• Before going to floor plan we can check all the sanity


checks
• Check_design
• Check_timing
• Check_library
• In real time if we get any errors in these checks ,then
we report to synthesis team.
• Sometimes we face issues for placing ports, it can
place entire die area why? because of that place
is not sufficient for ports placement so that time
we can carefully select the area(coordinates) and
place the ports.
• Create_pin_guide –boundary {{} {}} –name I/o
[all_inputs/outputs]
• Command for removing and ports

FLOORPL  Remove_pin_guide i /o # i is the input


& o output
AN  Remove_terminals [get_terminals -
of_objects [all_inputs/outputs]]
• Mmmc path
/data/pd/40lp/user_PR/user3_icc2_bil/lab2_floorp
lan/scripts/
• Constraints path
/data/pd/40lp/user_PR/user3_icc2_bli/lab56_setu
p/ORCA_TOP_constraints/ORCA_TOP_m………
• Place the macros using macro placement
guidelines only.
• Macros are placed according to fly-line
analysis (then they are placed near each other
to reduce the delay).
1.macro to ports
2. macro to macro
3. macro to standard cell.
• Macro placement is done according to
logical hierarchical
• macros must be placed at the boundary of
the block.
• Macro pins face towards the core area only.
(to avoid net detour)
• At least one pair of metal layer tracks must be
between two macros.
• Try to put hard blockages or partial
blockages in the area where there are gaps in
between Macros.
• Apply keep out margin around the Macros to
avoid congestion around the macros.
• Create voltage area
• With the help of
command create
voltage area.
• Create_voltage_area -
power_domains
PD_RISC_CORE –region
{{}{}} –guard_band
{{}}
• And also give sufficient
for placing std cells in
that region
• If we get any drc errors after
#check_pg_drc, we can use this
command for auto connectivity
#connect_pg_net –automatic
• If we get any missing vias
 create_pg_vias –nets
Power {VDD/VSS} –from_layers M8
plan –to_layers M7 –drc no_check.
 We check it on error
browser ,it shows that metal
layer where we get that error
suppose M7 layer got error
then we can take higher
metal layer as m8 & lower
metal layer as m7
• After power plan if we get any legality errors,
floating errors, missing via errors, continuity
violations.
• for these type of errors, Moving macros
(upside, downside, left or right) it’s means
giving sufficient spacing between macro to
macro . It will reduce max all type of errors.
• Before going to placement stage all errors
must be zero(0).
placement
• In this placement we can check cell density , pin density
and grc
• If any errors are there it can highlight the hotspot area
• cell density (partial blockage)
 In gui mode we give pb(partial blockage) or
by command
 It will block the area how much percentage
we give and remaining will be for routing.
• Pin density (keep out margin)
 in gui mode we give keep out margin or by
command
 no other std cells are present in that region
• If we get any grc error we can do floorplan again.
• Cell density
• Pin density
• grc
• After that we can perform
checks
• If overflow is greater than
0.3% you may have routing
issues
• Check legality clean
cts
• After that we can proceed to cts
• Source the files of cts
• Analyze the reports
• If we get any drv’s we can fix manually (using shift
keys).
Routing
• Source the files of routing
• If we get any drv’s we can fix manually

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