Digital Computer Structure

381-1-0103
1

Lecture 7 – Serial
Communication

Shlomo Greenberg

Web site: http://moodle2.bgu.ac.il

 Course Focus: Computer
2
Structure
Examples:
Intel 8251A Cloc Powe
TI/ARM k r
UART
HW
Communica Timer /
I2C tion Watchdog
Controller Memor

Memory
SPI

Virtual
Cache
y

Memory
Primary

Devices
MMU
Central Control
Interrupt Processin ler /
Decode
Controller g Unit r
(CPU)
IO Secondar
DMA Control y
Controller ler / Memory
Process Devices
IO
Bus Boot / or Devices
Configurati
on
 Syllabus (7/9)
3

 Basic Components of the digital computer:

CPU, IO, Memory and buses
 Hardware accelerators: Interrupt Controller,
DMA Controller
 Serial Communication Controller
 Background
 Open System Interconnection (OSI)
 Communication Types
 Communication Controller - General
 UART device, RS232 and RS485 protocols
 Current loop
 I2C and SPI protocols
 Intel 8251A and TI MSP430x Communication
Controllers
4
Serial Communication -
General
 Communication
5

 Transferring information over a distance

 Human Communications, examples:
 auditory (language, music)
 visual (body language, smoke signals,
writing)
 Machine Communications:
 Requires a shared symbol set that can be
encoded and transmitted as an
electromagnetic signal in a medium,
received and understood
 Symbol set: 0/1, Morse Code

 Networking
6

 Facilitating the communications among

multiple (potentially a large number of)
parties
 Solutions:
 Complete mesh
 Allusers connected back-to-back with one
another
 Infeasible

 Broadcast
 Switching
 Broadcast-Based Networks
7

 All users share a broadcast medium,

which is used even for one-to-one
communications
 Examples: Ethernet, Token ring.
 The main issue is Medium Access
Control (MAC).
 When two nodes wish to broadcast at the
same time, who gets “right of the road”?
 Scalability problem
 # of users limited by the bandwidth of the
shared medium
 Switching-Based Networks
8

 Uses intermediate nodes, called switches

or routers, to relay messages.
 One main issue is routing, the task of
finding a path form the source of a
message to the destination.
 LAN vs. WAN
9

 Local Area Networks (LANs)

 Small Area (e.g., a building)
 Privately owned media
 Typically based on broadcast, but switching
is emerging (ATM LANs, switched Ethernet)
 Wide Area Networks (WANs)
 Large Area (country or global)
 Due to large areas and large numbers of
users, WANs must use switching
technologies.
 Also, MAN (Metropolitan AN), SAN
 Networking Standards -
10
Motivation
 Reasons for networking standards
 allow different computers to communicate
 decrease price through economies of scale
 Disadvantages of standards
 Tend to freeze technology: by the time the
standard is developed, reviewed, agreed
upon, and distributed, better technologies
become available
 Often multiple, conflicting standards for the
same thing
 Networking Standard
11
Organizations
 ISO (International Organization for
Standardization)
 a voluntary organization that produces
standards for “everything” including network
protocols.
 Well known for its OSI (Open Systems
Interconnection) networking model.
 ITU (International Telecommunication
Union)
 UN treaty organization comprising primarily
the PPT (Postal, Telegraph, and telephone)
authorities of member countries.
 Standard Organizations –
12
Cont.
 ANSI (American National Standards
Institute)
 non-profit non-governmental organization
composed of manufacturers, users and
carriers
 C/C++ languages
 IEEE (Institute of Electrical and
Electronic Engineering)
 professional society and member of ANSI
 known for standards for LANs
 IEFT (Internet Engineering Task
 Networking Layers
13

 Network functions are organized as a

series of layers, in order to reduce
complexity.
 Each layer builds upon the one beneath it
and provides services to the one above it.
 Between each layer is an interface.
 Well-defined layering minimizes information
flows across layer boundaries and
encourages modulization
14
Open Systems
Interconnection
 Open Systems
15
Interconnection (OSI)
 a seven layer model defined by ISO.
 a conceptual model that characterizes
7.
and standardizes the communication Application
functions of a telecommunication or
6.
computing system without regard to Presentatio
their underlying internal structure and n
technology. 5. Session
 Its goal is the interoperability of diverse 4.
communication systems with standard Transport
protocols. 3. Network
 The model partitions a communication 2. Data link
system into abstraction layers 1. Physical
 Open Systems
16
Interconnection (OSI)
Layer PDU Function
Reliable transmission of data
frames between two nodes
connected by a physical
2. Data
Frame layer
link
– error detection/correction
– reliability
Medi – flow control
a
Laye Transmission and reception
rs of raw bit streams over a
physical medium
1. – analog and digital
Bit
Physical transmission
– a definition of the 0 and 1
 Open Systems
17
Interconnection (OSI)
Layer PDU Function
Structuring and managing a
multi-node network,
including addressing, routing
and traffic control
Medi – Routing: determining the
a 3. path from the source of a
Packet
Laye Network message to its destination
rs – Congestion Control:
handling traffic jams
– Internetworking of both
homogeneous and
heterogeneous networks.
 Open Systems
18
Interconnection (OSI)
Layer PDU Function
Reliable transmission of data
segments between points on
a network (end to end, or
host to host, connections),
including segmentation,
acknowledgement and
Segmen multiplexing
Host
4. t/ – Packetization: cut the
Laye
Transport Datagra messages into
rs
m smaller chunks (packets)
– An ensuing issue is
ordering: the
receiving end must make
 Open Systems
19
Interconnection (OSI)
Layer PDU Function
Managing communication
sessions, i.e. continuous
exchange of information in
the form of multiple back-
Host
5. and-forth transmissions
Laye Data
Session between two nodes
rs
– user–to–user connection
– synchronization,
checkpoint, and error
recovery
 Open Systems
20
Interconnection (OSI)
Layer PDU Function
High-level APIs, including
resource sharing, remote file
7.
access
Application
– file transfer, email, WWW,
and so on
Translation of data between a
Host networking service and an
Laye Data application; including
rs character encoding, data
6.
compression and
Presentatio
encryption/decryption
n
– data
representation/compression
 Open Systems
21
Interconnection (OSI)
Layer Examples of Protocols
7. HTTP, SMTP, FTP, RTP, IRC, SNMP, SIP,
Application DNS, DHCP
6. MIME, ASCII, Unicode, SSL
Presentation
5. Session ASP, PPTP, SSH, NFS, RPC, SOCKS
4. Transport TCP, UDP, SCTP, DCCP
3. Network IP (IPv4, IPv6), ICMP, IPX
2. Data link Ethernet, Token ring, FDDI
1. Physical E1, 10Base-T, RS-232, DSL, SONET
 Shortcomings of the OSI
22
Model
 All layers do not have the same size and
importance
 session and presentation layers (5-6)
seldom are present
 data link, network, and transport layers (2-
4) often very full
 Little agreement on where to place
various features
 Encryption, network management
 Internet Reference Model
23

7.
4.
3.
1,2.
24 Communication Types
 Serial vs. Parallel
25
Communication
 Microprocessors are based mostly on 8-
bit registers. Thus, their fastest I/O is 8-
bit parallel ports.
 But, wiring cost of a long distance
communication is very expensive if you
carry 8-wires.
 Remedy is to transfer data serially in bits
instead of in bytes or words.
 Wired vs. Wireless
26

 Computer networks for the home and small business

can be built using either wired or wireless technology.
 Wired Ethernet has been the traditional choice in
homes, but Wi-Fi and other wireless options are
gaining ground fast. Both wired and wireless can claim
advantages over each other; both represent viable
options for home and other local area networks (LANs).
Wired Wireless
Installation Moderate difficulty Easier, but beware
interface
Cost Less More
Reliability High Reasonably high
Performanc Very good Good
e
Security Reasonably good Reasonably good
 Simplex vs. Duplex
27

 In Simplex Mode data flow is in one

direction only.

 In Half Duplex Mode data flows in one

direction, at a given time, A protocol and
switches connect the devices both to
receive and also to transmit.

 In Full Duplex mode, transmitted data

and received data goes simultaneously
through two channels.
 Synchronous vs.
28
Asynchronous
 In synchronous transmission an explicit clock
signal describes the instants of valid data.
 A single data bit is sent at each clock.
 Minimum three signal lines required for full duplex:
Receive-DATA, Transmit-DATA, and CLOCK.
 In asynchronous transmission clock is
derived using a-priory parameters and a start
bit (or a start sequence).
 Transfer rate known, internal clock starts to pulse
with the start bit, at the known transfer rate.
 Only two signal lines required for full duplex:
Receive-DATA and Transmit-DATA
 Synchronous vs.
29
Asynchronous
 Synchronous
 Sync at the beginning and then transfer of
all data

 Asynchronous
 Sync at the beginning of each datum
 Asynchronous Transmission
30
Start and Stop Bits
 Start bit is required to synchronize the
internal clock of receiver.
 Stop bit is required to test the clock
frequency.
 Only DATA is transmitted, internal clock
is generated locally.

Data is 0b01100101 = 0x65. It is ASCII ‘e’

 Asynchronous
31
Communication System
 Computers may be connected to each
other at COM port or TTL signal levels as
well.
 Centralized vs. Distributed
32

 Centralized: one master (master is the

only initiator), many slaves
 Distributed: many initiators, many slaves
 Centralized Communication
33
Topologies

Multi-drop Daisy-chain

Highest
Loop Priority
 Distributed Communication
34

 Example – Ethernet
 Multiple access communication
 Protocol is CSMA/CD
 CS – Carrier Sense - Is the line silent?
 MA – Multiple Access - using random wait
time to initiate transaction. Collisions are
probable.
 CD – Collision Detection
 Data Transfer Rate
35

 Both devices shall know the data transfer

rate of the communication to synchronize
the internal clocks correctly.
 Data transfer rate is measured in BAUD
 Baud = bit/second (including start, stop,
data, parity etc.)
 kilo Baud = 1,000 Baud (not 1024 Baud)
 Mega Baud = 1,000,000 Baud
 Baud Rate Calculations
36

 If each bit takes T seconds, the baud

rate is B=1/T.
 Standard baud rates are 150, 300, 600,
1200, 2400, 4800, 9600, 19200, etc.
 Baud rate tolerance for a 10-bit frame is
5%.
 Example: T=209us => B=1/T=4785
Baud
 It is 4800 Baud within 5% tolerance.
 Packet transmission time
37

 If a system sends a packet of 50 bytes at

1200 Baud, using 8-data, no-parity, one
stop bits, what is the transmission time
of the whole packet:
 1-byte frame is 1-start + 8-data + 1-stop
bit = 10 bits/byte.
 Packet is transferred by 50 x 10 bits = 500
bits on the serial communication line.
 Tpacket = 500 bits / 1200 Baud = 0.417sec =
417 ms
38 Communication Controller
 Communication Controller
39

 A communication controller is small computer

used to manage the communication of
input/output (I/O) data in a network, host
machine or computer. A communication controller
facilitates user tracking of all network activities
and saves all data on a mainframe computer.
 Controllers convert parallel data into serial data
for network transfer and handle other network
tasks, including error control, data compression,
proper routing and security parameters.
 A communication controller is also known as a
front-end processor or a communications
processor.
 Communication Controller
40
Uses
 A communication controller is used for a variety
of reasons, including the following:
 Create communication links used to manage data
transmission between different devices and
channels
 Error detection and correction
 Data routing via different network devices, such as
routers and bridges
 Buffering to store incoming and outgoing data
 Providing network nodes/terminals for session
connections
 Manage data flow
 Communication Controller
41

 RS-232 protocol
 “Slow” speed communication protocols:
SPI, I2C, USART, and more
 “High” speed communication protocols:
Serial Rapid IO (SRIO), PCI Express
(PCIe), Common Protocol Radio Interface
(CPRI), and more
42 UART Device
 UART
43

 A processor may transmit/receive data in serial

format without any extra hardware.
 But it costs to the processing time of the processor.
 A UART (Universal Asynchronous Receiver
Transmitter) is a hardware device that shifts out
data bits to transmit a data byte, and also
shifts-in data bits to receive a data byte.
 This is not a high speed serial interface,
common speeds vary between 50bps to
460.8Kbps.
 First single-chip UART on general sale was
introduced in 1971, called WD1402A.
 Serial to Parallel Conversion
44

 Serial to Parallel
conversion using
a Universal
Asynchronous
Receiver
Transmitter:
 UART / USART
45

 A UART is a computer hardware device for

asynchronous serial communication in which the data
format and transmission speeds are configurable.
The electric signaling levels and methods (e.g.
differential signaling) are handled by a driver circuit
external to the UART.
 UART-s are commonly used in conjunction with
communication standards such as RS-232, RS-422 or
RS-485.
 A UART is usually an individual (or part of an)
integrated circuit (IC) used for serial communications
over a computer or peripheral device serial port.
 A related device, the Universal
Synchronous/Asynchronous Receiver/Transmitter
(USART) also supports synchronous operation.
 Transmitting / Receiving
46
Serial Data
 UART takes bytes of data and transmits the
individual bits in a sequential fashion. At the
destination, a second UART re-assembles the
bits into complete bytes. Each UART contains a
shift register, which is the fundamental method
of conversion between serial and parallel forms.
 Communication may be simplex (in one
direction only, with no provision for the receiving
device to send information back to the
transmitting device), full duplex (both devices
send and receive at the same time) or half
duplex (devices take turns transmitting and
receiving).
 Electrical Signals
47

 UART usually does not directly generate or receive

the external signals used between different items of
equipment. Separate interface devices are used to
convert the logic level signals of the UART to and
from the external signaling levels.
 External signals may be of many different forms:
 Voltage signaling, e.g. RS-232, RS-422 and RS-485.
 Current in current loops, as was used in telegraph circuits.
 Without electrical wires. E.g. optical fiber, IrDA (infrared),
and (wireless) Bluetooth in its Serial Port Profile (SPP).
 Modulation of a carrier signal (with or without wires). E.g.
modulation of audio signals with phone line modems, RF
modulation with data radios, and the DC-LIN for power
line communication.
 Data Framing
48

 IDLE (i.e. no data) state is high-voltage, or

powered.
 Each character is sent as a logic low start bit, a
configurable number of data bits (usually 8, but
users can choose 5 to 8 or 9 bits depending on
which UART is in use), an optional parity bit if
the number of bits per character chosen is not 9
bits, and one or more logic high stop bits.
 In most applications the least significant data bit
(the one on the left in this diagram) is transmitted
first, but there are exceptions (such as the IBM
2741 printing terminal).
 Data Framing
49

 The start bit signals the receiver that a new character is

coming.
 The next five to nine bits, depending on the code set
employed, represent the character.
 If a parity bit is used, it would be placed after all of the
data bits.
 The next one or two bits are always in the mark (logic
high, i.e., '1') condition and called the stop bit(s). They
signal the receiver that the character is completed.
 Since the start bit is logic low (‘0’) and the stop bit is logic
high (‘1’) there are always at least two guaranteed signal
changes between characters.
 If the line is held in the logic low condition for longer than
a character time, this is a break condition that can be
detected
 UART Parameters
50

 Transmitting and receiving UARTs must be set for the

same bit speed, character length, parity, and stop bits
for proper operation
 Parameters include:
 Baud rate (transmission rate in bits per second). E.g.
19.2Kbps.
 Data width (number of bits per character)
 Start bit pulse width – pulse width of the ‘0’
 Checked in the middle of the cycle – less error prone as devices
are asynchronous
 Stop bit pulse width – pulse width of the ‘1’
 Finish word in logic “1” so Idle state is achieved, waiting for
start bit
Parity bit (yes/no) – If exists, odd/even

Remark: Cycle time in TX and RX is identical because of constant bau
 UART is part of OSI
51

OSI UART
 Several Common Protocols
52
using UART
 Special Transceiver
53
Conditions
 Overrun error - the receiver cannot process the
character that just came in before the next one
arrives
 Underrun error - the UART transmitter has
completed sending a character and the transmit
buffer is empty
 Framing error - the designated "start" and "stop"
bits are not found
 Parity error - the parity of the number of 1 bits
disagrees with that specified by the parity bit
 Break condition - the receiver input is at the
"space" (logic low, i.e., '0') level for longer than some
duration of time, typically, for more than a character
time
 UART in MODEM-s
54

 MODEM-s for PC-s that plug into a motherboard slot

must also include the UART function on the card.
 The original 8250 UART chip shipped with the IBM PC
had a one character buffer for the receiver and the
transmitter each, which meant that communications
software performed poorly at speeds above 9.6Kbps,
especially if operating under a multitasking system
or if handling interrupts from disk controllers.
 High-speed modems used UART-s that were
compatible with the original chip but which included
additional FIFO buffers, giving software additional
time to respond to incoming data.
55 RS-232 Protocol
 RS-232
56

 RS-232 is a standard for serial communication

transmission of data. It formally defines the signals
connecting between a DTE (Data Terminal
Equipment) such as a computer terminal, and a
DCE (Data Circuit-terminating Equipment or Data
Communication Equipment), such as a modem.
 RS-232 standard is commonly used in computer
serial ports. The standard defines the electrical
characteristics and timing of signals, the meaning
of signals, and the physical size and pinout of
connectors.
 RS-232 was first introduced in 1960. Current
version of the standard is TIA-232-F issued in 1997.
 RS-232 – Limited Usage
57
Today
 An RS-232 serial port was once a standard feature of a PC,
used for connections to modems, printers, and other
peripheral devices.
 RS-232, when compared to other serial interfaces such as
RS-422, RS-485 and Ethernet, has low transmission speed,
short maximum cable length, large voltage swing, large
standard connectors, no multipoint capability and limited
multidrop capability.
 In modern PC-s, USB has displaced RS-232. Many computers
must use either an external USB-to-RS-232 converter or an
internal expansion card to connect to RS-232 peripherals.
 Nevertheless, thanks to their simplicity and past ubiquity,
RS-232 interfaces are still used - particularly in industrial
machines, networking equipment, and scientific
instruments.
 RS-232 – Scope of Standard
58

 The Electronic Industries Association (EIA) standard RS-

232-C as of 1969 defines:
 Electrical Specifications - Electrical signal characteristics
such as voltage levels, signaling rate, timing, and slew-rate of
signals, voltage withstand level, short-circuit behavior, and
maximum load capacitance.
 Mechanical Specifications - Interface mechanical
characteristics, pluggable connectors and pin identification.
 Logical Specifications - Functions of each circuit in the
interface connector.
 The standard does not define the character encoding
(e.g. ASCII), the framing of characters (start or stop bits,
etc.), transmission order of bits, bit rate (only that it is
less than 20Kbps), or error detection protocols.
 RS-232 - Socket Pins
59

 The standard describes two kinds of

sockets:
 DTE: Device Terminal Equipment
 Computer Terminal, etc.
 Active; Master
 DCE: Device Communication Equipment
 Printers, MODEM, etc.
 Passive; Slave
 Equipment Connections Options:
 DTE is connected to DCE without crossing.
 DTE is connected to DTE cross-wired.
 Full duplex
 Both synchronous and asynchronous
transmissions are supported
Notice that TXD is an output pin in DTE but an input pin in
 RS-232 - Electrical
60

 Single ended Data Control Voltage

Circuits Circuits
 Maximum open-
0 Asserted +3V to
circuit level of 25V (=“space”) +15V
 Need to use devices 1 De- -15V to -3V
which convert device (=“mark”) asserted
voltage level (e.g.
+/-5V - the usual)
from/to the interface
voltage level (e.g.
+/-12V).
 E.g. LM1488, LM1489

Driver circuit for RS232 send and receive lines

 RS-232 - Mechanical
61

 Connector:
DB-connector with 25 pinsDCE
DTE
(Femal
(only 8 are usually used) e)
(Male)
PGN Protective Ground – Reduces
D noise
TXD Transmit Data
RXD Receive Data
RTS Request to Send
CTS Clear to Send
GND Ground
DSR Data Set Ready
DTR Data Terminal Ready
RLSD Received Line Signal Detect
 RS-232 - Mechanical
62

 A minimal 3-wire RS-232 connection consisting only

of transmit data, receive data, and ground, is
commonly used when the full facilities of RS-232 are
not required.
 Even a two-wire connection (data and ground) can
be used if the data flow is one way (for example, a
digital postal scale that periodically sends a weight
reading, or a GPS receiver that periodically sends
position, if no configuration via RS-232 is necessary).
 When only hardware flow control is required in
addition to two-way data, the RTS and CTS lines are
added in a 5-wire version.
 RS-232 - Mechanical
63

 The standard does not define a maximum

cable length, but instead defines the maximum
capacitance that a compliant drive circuit must
tolerate.
 A widely used rule of thumb indicates that
cables more than 15 m (50 ft) long will have
too much capacitance, unless special cables
are used:
 Baud rate is a minimum of 19.2Kbps for a line of 50ft
 Minimum transition time between logical levels
– less than 4% than the latency of 1bit.
 T = 1/19200 * 0.04 = 2.1us
 RS-232 – Modem
64
Handshaking
 Flow Control Signals:
 RTS: Request to Send (=> DTE sends char,
DTE requests the DCE prepare to transmit
data)
 CTS: Clear to Send (=> DCE accepts RTS,
DCE is ready to accept data from the DTE)

 Device Status Signals:

 DTR: Data Terminal Ready (=> DTE is OK,
i.e. DTE is ready to receive, initiate, or
continue a call)

 UART and RS232
65

 UART (or USART) is, essentially, a serial communications

interface. The "universal" part means that it can be configured
to support many different specific serial protocols. The term is
generic, and does not represent a specific standard. At
minimum it means that it has a TX and an RX line, which sends
a serial data stream and receives a serial data stream.
 RS-232 is A standard defining the signals between two devices,
defining the signal names, their purpose, voltage levels,
connectors and pinouts.
 This is a specific interface standard that allows for equipment
interoperability.
 While two pieces of hardware may have UARTs, you don't know that
they'll connect without damage, or communicate properly unless you
know they have the same pinout and voltage standards, or include a
converter or specially wired cable specific to the interconnection of
these two specific devices. To avoid the need for special converters
or cables, the manufacturers may choose to follow the RS-232
standard.
 UART and RS232 – Cont.
66

 However, neither the UART, nor the RS-232 standard define what is
sent on the TX and RX lines. Generally, when people use RS-232,
they use a simple 8 bit NRZ encoding with one start bit and one stop
bit. Most equipment today manufactured uses this encoding, but
there's no requirement to do so. You can find older equipment that
includes parity bits, or uses 7 or 9 bits. The UART can be configured
to support these various protocols on its TX and RX lines.
 UARTs do not typically interface directly with RS-232. You will need to
convert the output of the UART to the +/-12V standard that RS-232
requires. A complete RS-232 interface will typically involve both a
UART and an RS-232 level converter. The RS-232 standard includes
the definition of several other signaling pins besides TX and RX,
which you may need to use depending on the equipment you need to
connect to. These will also need to be level converted, and your
UART may, or may not, support these signals. If it does not you will
have to control them with your software/firmware directly.
 So while a UART may help you implement an RS-232 interface, it is
not an RS-232 interface itself.
67 RS-485 Protocol
 RS-485
68

 RS-485, also known as TIA-485(-A), EIA-485, is a standard defining

the electrical characteristics of drivers and receivers for use in
serial communications systems. RS-485 only specifies electrical
characteristics of the generator and the receiver. It does not
specify or recommend any communications protocol, only the
physical layer.
 Electrical signaling is balanced, and multipoint systems are
supported.
 RS-485 supports inexpensive local networks and multidrop
communications links, using a differential balanced line over
twisted pair (as in RS-422).
 It is generally accepted that RS-485 can be used with data rates
up to 10 Mbps and distances up to 1,200 m (4,000 ft), but not at
the same time. A rule of thumb is that the speed in bps multiplied
by the length in meters should not exceed 108.
 RS-485 is an enhancement to RS-422. RS-485 is multi-point and
not only multi-drop. RS-422 does not allow multiple drivers but
only multiple receivers.
 RS-485 – Electrical
69

 Uses balanced or differential pair:

binary “1” (i.e.

OFF)
(Voa–Vob <
−200 mV)
binary “0” (i.e. ON)
(Voa–Vob >
 Logical data is based on the difference between
+200 mV)the
pair and not vs. common ground
 Advantages
 Electromagnetic noise impacts both wires the same way,
hence – differential voltage is not impacted
 Voltage drop would impact both wires the same way,
hence – differential voltage is not impacted
 High throughput and long wires are supported
 RS-485 – Cont.
70

 Allows the usage of more than one transceiver (up to 32

transceivers)
 Repeater can make the distances even longer
 RS-485, like RS-422, can be made full-duplex by using four
wires. However, Since RS-485 is a multi-point specification,
this is not necessary in many cases. RS-485 and RS-422
can interoperate with certain restrictions.

RS-485 multi-
drop half-
duplex
network
structure:
 RS-485 – Waveform
71
example
 The diagram below shows potentials of
the '+' and '−' pins of an RS-485 line
during transmission of one byte (0xD3,
least significant bit first) of data using an
asynchronous start-stop method (e.g.
UART)
72 4-20 mA (Current Loop)
 Current Loop
73

 In electrical signaling, an analog current loop is used

where a device must be monitored or controlled
remotely over a pair of conductors. Only one current
level can be present at any time.
 A major application of current loops is the industry
standard 4-20 mA current loop for process control
applications, where they are extensively used to carry
signals from process instrumentation to PID controllers,
SCADA systems, and Programmable logic controllers.
 These loops have the advantages of simplicity and
noise immunity, and have a large international user
and equipment supplier base.
 Various Automation Protocols may replace analog
current loops, but 4-20 mA is still a principal industrial
standard.
 Process control 4-20 mA
74
loops
 “1” is a 20mA current; “0” – 4mA
 Every direction (TX/RX) requires 2 wires
 Active side (usually computer) drives
current on wire
 Passive side tests the wire for current
 No specific connector; no hand-shaking
 Optical coupler (LED and photo-
transistor) convert current to voltage
and isolate the computer from the
device
 Current Loop – Cont.
75
 Current Loop – Cont. 2
76

 Serial data can be transmitted for

distances up to 1500 feet at data rates
up to 9,600 baud
 Current Loop - Advantages
77

 The loop can often power the remote device, with

power supplied by the controller, thus removing need
for power cabling.
 The "live" zero of 4 mA allows powering of the device even
with no process signal output from the field transmitter.
 The accuracy of the signal is not affected by voltage
drop in the interconnecting wiring.
 high noise immunity as it is low impedance circuit
usually through twisted pair conductors.
 self-monitoring; currents less than 3.8 mA or more
than 20.5 mA are taken to indicate a fault.
 It can be carried over long cables up to the limit of the
resistance for the voltage used.
 Easy conversion to voltage using a resistor.
78 I2 C
 I2C
79

 I²C (Inter-Integrated Circuit), is:

 multi-master
 multi-slave
 Two-wire
 Packet-switched
 Open-drain single-ended
 Half-duplex
 Serial computer bus
 Invented by Philips Semiconductor in 1982
 Typically used for attaching lower-speed
peripheral integrated circuits (IC-s) to processors
and microcontrollers in short-distance, intra-
board communication
I2C Connectivity
 Multi-master, two wire bus:
 One data line (SDA)
 One clock line (SCL)
 Master controls clock for slaves
 Each connected slave has a unique 7-bit address
 Bitrate: 0.1 / 0.4 / 1.0 / 3.4 / 5.0 Mbps (depending
on mode)
Protocol
 Transfers are byte oriented, MSB first
 Start: SDA goes low while SCL is high
 Master sends address of slave (7-bits) on
next 7 clocks
 Master sends read/write request bit
 0-write to slave
 1-read from slave
 Slave ACKs by pulling SDA low on next
clock
 Data transfers now commence
Master-to-Slave Data
Transfer
 Clock is controlled by master
 Data is written to slave on next 8 clock
pulses
 Data receipt is ACKed by slave on 9th
pulse by pulling SDA low
 When slave releases SDA master can
send next byte
 Master will eventually set a Stop
condition by making a low to high
transition on SDA with SCL is high
Complete I2C Transfer
Master Writes to Slave
Master Reads from Slave
I2C Extensions
 10 bit addressing (up to 1,024
addresses)
 Fast mode – up to 400 Kbps
 High-Speed – up to 3.4 Mbps
87 SPI
SPI (Serial Peripheral
Interface)
 Developed by Motorola
 Also known as MicroWire (National
Semiconductor), QSPI (Queued),
MicrowirePlus
 Synchronous Serial Communication

SCLK Serial Clock (output from master).

MOSI Master Output Slave Input, or Master Out Slave In (data output
from master).
MISO Master Input Slave Output, or Master In Slave Out (data output
from slave).
SS Slave Select (often active low, output from master).
SPI Configuration
 Primarily used for
serial communication
between a host
processor and
peripherals.
 Can also connect two
processors via SPI
 SPI works in a master-
slave configuration
with the master being
the host
microcontroller for
example and the slave
being the peripheral
SPI Operation
 For SPI, there are Serial Clocks (SCLK), Chip
Select lines (CS), Serial Data In (SDI) and Serial
Data Out( SDO)
 There is only one master. The number of slaves
depends on the number of chip select lines of the
master.
 Synchronous operation, latch on rising or falling
edge of clock, SDI on rising edge, SDO on falling
edge
 Operates in 1 to 2 MHz range
 Master sends out clocks and chip selects -
Activates the slaves it wants to communicate
with
Master Slave Setup
 In this
Multiple
setup,Independent
there are 3 slave
Slavedevices.
Configuration
The SDO
lines are tied together to the SDI line of the
master.
 The master determines which chip it is talking to
by the CS lines. For the slaves that are not being
talked to, the data output goes to a Hi Z state
Master Slave Setup - Multiple
slave cascaded (Daisy-chain)

 In this example, each slave is cascaded so

that the output of one slave is the input of
another. When cascading, they are treated
as one slave and connecting to the same
chip select
 Operation
93
 The master then selects the slave device with a logic level 0 on the
select line (CS).
 During each SPI clock cycle, a full duplex data transmission occurs. The
master sends a bit on the MOSI line and the slave reads it, while the
slave sends a bit on the MISO line and the master reads it. This
sequence is maintained even when only one-directional data transfer is
intended.
 Transmissions normally involve two shift registers of some given word
size, such as 8b, one in the master and one in the slave. Data is usually
shifted out with the most-significant bit first, while shifting a new least-
significant bit into the same register. At the same time, Data from the
counterpart is shifted into the least-significant bit register. After the
register bits have been shifted out and in, the master and slave have
exchanged register values. If more data needs to be exchanged, the
shift registers are reloaded and the process repeats. When complete,
the master stops toggling the clock signal, and typically deselects the
slave.
 Every slave on the bus that has not been activated using its chip select
line must disregard the input clock and MOSI signals, and must not drive
MISO
 Operation
94

 When data is sent from the master to a slave, it’s sent on a

data line called MOSI. If the slave needs to send a response
back to the master, the master will continue to generate a
prearranged number of clock cycles, and the slave will put the
data onto a third data line called MISO.
 “prearranged” - Because the master always generates the clock
signal, it must know in advance when a slave needs to return data
and how much data will be returned.
 This is very different than asynchronous serial, where random
amounts of data can be sent in either direction at any time. In
practice this isn’t a problem, as SPI is generally used to talk to
sensors that have a very specific command structure.
 For example, if you send the command for “read data” to a device,
you know that the device will always send you, for example, two
bytes in return (In cases where you might want to return a variable
amount of data, you could always return one or two bytes
specifying the length of the data and then have the master
retrieve the full amount.)
95
SPI Timing Diagram - EEPROM
Read
Comparison of Serial
Interfaces
98 Intel 8251A Communication Controller
Introduction
 8251A is a USART (Universal Synchronous
Asynchronous Receiver Transmitter) for serial
data communication.
 Programmable peripheral designed for
synchronous /asynchronous serial data
communication, packaged in a 28-pin DIP.
 Receives parallel data from the CPU & transmits
serial data after conversion.
 Also receives serial data from the outside &
transmits parallel data to the CPU after
conversion.
 Communication Controller
100
8251A
 Synchronous and Asynchronous Operation
 Synchronous – 5..8 bit characters; internal or
external character synchronization; automatic
sync insertion
 Asynchronous – 5..8 bit characters; clock rate –
1, 16, or 64 times baud rate; break character
generation; 1, 1.5 or 2 stop bits; false start bit
detection; automatic break detect and handling
 Baud rate – DC to 64K baud
 Full duplex, double buffered, transmitter and
receiver
 Communication Controller
101
8251A
 Error detection – parity, overrun and
framing
 Fully compatible with 8080/8085 CPU
 28-pin DIP package
 All inputs and outputs are TTL
compatible
 Single +5V supply
 Single TTL Clock
Pin Diagram
Block diagram of the 8251
USART
Transmitter

Receiver
Data Bus Buffer
 8b data bus used
to read or write
status, command
word or data
from or to the
8251A
Read/Write Control Logic
 Interfaces the chip
with MPU, determines
the functions of the
chip according to the
control word in the
control register &
monitors the data
flow
 Includes:
 Six input signals
 Three buffer registers:
 control register
 status register
 Data register
Control Logic: Input signals
 CS (Chip Select): When signal goes low, the 8251A is
selected by the MPU for communication.
 C/D (Control/Data): When signal is high, the control or
status register is addressed; when it is low, data buffer
is addressed (Control register & status register are
differentiated by WR and RD signals).
 WR: When signal is low, the MPU either writes in the
control register or sends output to the data buffer.
 RD: When signal goes low, the MPU either reads a
status from the status register or accepts data from
data buffer.
 RESET: A high on this signal reset 8252A & forces it
into the idle mode.
 CLK: Clock input, usually connected to the system clock
for communication with the microprocessor.
Control Logic: Control
Register
 16-bit register for a control word.
Consists of two independent bytes:
 Mode word: Specifies the general
characteristics of operation such as baud,
parity, number of bits etc.
 Command word: Enables the data
transmission and reception.
 Register can be accessed as an output
port when the Control/Data pin is high.
 Control Register: Mode
108
Word
 Control Register: Command
109
Word
 Control Logic: Status
110
Register
 Checks the
ready status of
the peripheral.
 Status word in
the status
register
provides the
information
concerning
register status
and
 Control Logic: Data Register
111

 Used as an input and output port when

the C/D is low

CS C/ WR RD Operation
D
0 0 1 0 MPU reads data from the data
buffer
0 0 0 1 MPU writes data to the data buffer
0 1 0 1 MPU writes a word to control
register
0 1 1 0 MPU reads a word from status
register
1 X X X Chip is not selected for any
operation
Modem Control
 DSR (Data Set Ready): Checks
if the Data Set is ready when
communicating with a modem.
 DTR (Data Terminal Ready):
Indicates that the device is
ready to accept data when the
8251 is communicating with a
modem.
 CTS (Clear to Send): If its low,
the 8251A is enabled to
transmit the serial data
provided the enable bit in the
command byte is set to ‘1’.
 RTS (Request to Send Data):
Low signal indicates the
modem that the receiver is
ready to receive a data byte
from the modem.
 Transmitter – Block Diagram
113

 Accepts parallel data from MPU & converts them

into serial data.
 Has two registers:
 Buffer register: Holds eight bits
 Output register: Converts eight bits into a stream of
serial bits.
 Transmitter
114
Transmitter Structure
 The MPU writes a byte in the buffer register.
 Whenever the output register is empty; the contents
of buffer register are transferred to output register.
 Transmitter section consists of the following signals:
 TxD (Transmitted Data Output): Output signal to
transmit the data to peripherals
 TxC (Transmitter Clock Input): Input signal, controls
the rate of transmission.
 TxRDY (Transmitter Ready): Output signal, indicates
the buffer register is empty and the USART is ready to
accept the next data byte.
 TxE (Transmitter Empty): Output signal to indicate the
output register is empty and the USART is ready to
accept the next data byte.
 Transmitter Flow
116

 Unmask the interrupts

 Masking is used to stop transmitting and avoid
unnecessary interrupts (as TX_INT interrupt)
 Call CH-out using TX_INT interrupt
(TX_BUFFER_EMPTY interrupt) with buffer address
(pointer) and buffer length (data size)
 CH-out is writing to parallel register from the buffer
address, and then increment the pointer with data
size
 Data is moved from parallel register to shift
register
 Data is transmitter from shift register
 8251A Receiver – Block
117
Diagram
 Accepts serial data on the RxD pin and
converts them to parallel data.
 Has two registers :
 Receiver input register
 Buffer register
 Receiver
118
Receiver Structure
 When RxD goes low, the control logic assumes it is a
start bit, waits for half bit time, and samples the line
again. If the line is still low, the input register accepts
the following data, and loads it into buffer register at
the rate determined by the receiver clock.
 RxRDY (Receiver Ready Output): Output signal,
goes high when the USART has a character in the
buffer register & is ready to transfer it to the MPU.
 RxD (Receive Data Input): Bits are received serially
on this line & converted into a parallel byte in the
receiver input register.
 RxC (Receiver Clock Input): Clock signal that
controls the rate at which bits are received by the
USART.
 Receiver flow
120

 Start bit identification

 Read bit into input shift register (or
ignore if start bit is not identified)
 Parity check
 Stop bit identification
 Move entire data from shift register into
a parallel register
 Interrupt the CPU with RBF (Receiver
Buffer Full)
 CPU has 10 cycles before data is
 Receiver Error Types
121

 Overrun error – Data (in parallel register)

is overwritten before CPU has read it
 Parity error
 Frame error – either start/frame/stop are
not in the right size
122
Microcontroller Serial
Controller
TI – MSP430
ARM Microcontroller
 MSP430 Communication
123
Controller
 UART
 Two modulators support n/16 timings
 Auto baud rate detection
 IrDA encoder & decoder
 Simultaneous USCI_A and USCI_B (2 channels)
 SPI
 Two SPI (one on each USCI_A and USCI_B)
 Master and Slave Modes
 3 and 4 Wire Modes
 I2C
 Simplified interrupt usage
 Master and Slave Modes
 up to 400kbps
 Universal Serial
124
Communication I/F
 Two Individual Blocks:
 USCI_A:
 UART with Lin/IrDA support
 SPI (Master/Slave, 3 & 4 wire
mode)
 USCI_B:
 SPI (Master/Slave, 3 & 4 wire
mode)
 I2C (Master/Slave, up to
400kHz)
 Double Buffered TX/RX
 Baud-rate/Bit Clock
Generator:
 With Auto-Baud Rate Detect
 Flexible Clock Source
 RX glitch suppression
 DMA enabled
 Error Detection
 USCI Baud Rate Generator
125

 Oversampling Baud Rate Generation

 Two Modulators (UCBRSx and UCBRFx
select modulation pattern)
 RX sampled using BITCLK16
 SPI Example
126

 3 Wire Mode (MSP430 also supports 4-

wire mode)
 Clock Phase and Polarity configurable
 USCI: SPI Mode
127
 I2C Example
128
 USCI: I2C Mode
129

 7b/10b addressing
 Multi-master
transmitter/receiver
mode
 Slave
receiver/transmitter
mode
 Standard mode
(100kbps) and fast
mode (400kbps)
support
 Serial Communication -
130
Summary
 Serial communication has been
standardized using Open System
Interconnection (OSI) into 7 layers
 “Slow”, but extremely useful, serial
communication protocols include UART
(w/ RS-232 or RS-485), SPI and I2C
 Intel 8251A Communication Controller is
an example of a UART controller
 TI MSP430 Communication Controller is
an example of a UART/SPI/I2C controller
131 End of lecture 7
 References
132

 SPI, A. Maroudis, 2003

 I2C, D. Steflik, CS-423
 Chapter 7: Synchronous Serial: SPI and I2C interfaces, Lucio
Di Jasio, 2014
 8251A programmable Communication Interface, Ram, 2008
 DCS Lecture Notes of Shlomo Greenberg, Yaara Ben-Or, 2013
 DCS Lecture Notes of Shlomo Greenberg, Zeevik, 2008
 DCS communication, Shlomo Greenberg, 2003
 Wikipedia for RS-232 and RS-485 and on others
 OSI introduction, Yih Huang, 2006
 Intel 8251 datasheet, 1986
 Introduction to MSP430 Communication Interfaces, C.
Hernitscheck, 2006
 8251 USART and RS232C, D. Yagaysen, 2011