Digital Computer Structure

381-1-0103
1

Lecture 3 – I/O

Shlomo Greenberg

Web site: http://moodle2.bgu.ac.il

2
Hardware Timer -
Introduction
 Software and Hardware
3
Timers
 Everything is based on time
 Hence, the ability to time intervals or to generate
signals with a particular interval time are
common requirements
 software delay loop
 easy to insert; requires no additional hardware
 problem if other actions are to be done in parallel
 can be accurate if code is carefully timed
 hardware timer
 integrated into microcontroller or separate chip
 can be exact
 allows actions in parallel
 Hardware Timer Functions
4

 A microcontroller is required with

features to:
 Generate output signals with precise
parameters
 Measure the characteristics of input signals
 Count external events (e.g. I/O packets)
 Many designs require delay operators. A
timer can be used to create an
adjustable wait statement
 Additional usage:
 Watchdog
 Watchdog Timer
5

 A watchdog timer (WDT) is a

hardware timer that automatically
generates a system reset if the main
program neglects to periodically service
it. It is often used to automatically reset
an embedded device that hangs because
of a software or hardware fault.
 Watchdog – Cont.
6

 Identification of “not working” condition

 E.g.: During 1sec no keep-alive pulse exists.
 An implementation example:
working

Not-working

 Retriggerable circuit
 Timer is reset every predefined duration.
7
Intel 82C54 Hardware
Timer
 Intel 82C54 Hardware Timer
8

 Programmable Interval Timer which has three

independently programmable and functional 16-bit
counters
 Six programmable timer modes to be used as an event
counter, elapsed time indicator, programmable one-shot,
interrupt on terminal count (watchdog), and more
 Allows the generation of accurate time delays under
software control. Instead of setting up timing loops in
software, the programmer configures the 82C54 to match
his requirements and programs one of the counters for
the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and
variable length delays can easily be accommodated
 Gate count: 2,250 Gates
 Block Diagram
9

three-state, bi-directional, 8-bit buffer is used to

interface the 82C54 to the system bus

Chip Functional Diagram

 Counter Block Diagram
10

Count Register Counting Element

Output Latch
 Modes of Operation
11

 Interrupt on terminal count (watchdog,

event counting)
 Hardware re-triggerable one-shot
 Rate generator (divide by-N counter)
 Square wave (Baud rate generation)
 Software triggered one-shot
 Hardware triggered strobe
(retriggerable)
 Modes of Operation
12

 Interrupt on terminal count (watchdog, event

counting)
 After the Control Word is written, OUT is initially
low, and will remain low until the Counter reaches
zero. OUT then goes high and remains high until a
new count or a new Mode 0 Control Word is
written to the Counter.
 Hardware re-triggerable one-shot
 OUT will be initially high. OUT will go low on the
CLK pulse following a trigger to begin the one-
shot pulse, and will remain low until the Counter
reaches zero. OUT will then go high and remain
high until the CLK pulse after the next trigger
 Modes of Operation – Cont.
13

 Rate generator (divide by-N counter)

 OUT will initially be high. When the initial count has
decremented to 1, OUT goes low for one CLK pulse.
OUT then goes high again, the Counter reloads the
initial count and the process is repeated. Mode 2 is
periodic; the same sequence is repeated indefinitely.
For an initial count of N, the sequence repeats every
N CLK cycles.
 Square wave (Baud rate generation)
 OUT will initially be high. When half the initial count
has expired, OUT goes low for the remainder of the
count. Mode 3 is periodic; the sequence above is
repeated indefinitely. An initial count of N results in a
square wave with a period of N CLK cycles
 Modes of Operation – Cont.
14
2
 Software triggered one-shot
 OUT will be initially high. When the initial
count expires, OUT will go low for one CLK
pulse then go high again. The counting
sequence is “Triggered” by writing the
initial count
 Hardware triggered strobe (re-
triggerable)
 OUT will initially be high. Counting is
triggered by a rising edge of GATE. When
the initial count has expired, OUT will go
low for one CLK pulse and then go high
 Interrupt on Terminal Count
15
(Watchdog mode)
 After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so
for an initial count of N, OUT does not go high until N + 1
CLK pulses after the initial count is written.
 If a new count is written to the Counter it will be loaded
on the next CLK pulse and counting will continue from
the new count. If a two-byte count is written, the
following happens:
 Writing the first byte disables counting. Out is set low
immediately (no clock pulse required).
 Writing the second byte allows the new count to be loaded on
the next CLK pulse.
 This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
 HW Timers & Watchdog -
16
Summary
 Watchdog timers are hardware based
counters, with interrupt capabilities,
which are used to help monitor
execution of a program on the CPU.
 Hardware timers can be used for various
tasks, as they are accurate and software-
independent.
17 IO Devices - Introduction
 Typical Microcomputer
18
System

 Address, Control and Data

buses schematically.
 In many computers the
buses are made accessible
using connectors into
which cards are slotted
 IO Examples
19
 CPU-IO Communication
20

 CPU is able to output to and input from

memory using
 An address bus and decoder to select a
particular register in memory,
 A data bus to transfer the register’s
contents in or out of the CPU, and
 A control bus to carry signals such at
Read, Write, and Output Enable.
 CPU-IO Communication
21

Reading/Writing data to memory is always

performed in parallel, I/O to devices can be either
parallel or serial. Parallel has higher bandwidth, but
serial is necessary if the distance between CPU and
device substantial. Examples for fast serial links are
the USB and IEEE 1394 Firewire.
 I/O Devices - Background
22

 The I/O system allows peripherals to

provide data or receive results of
processing the data
 The Input / Output devices are regarded
as registers by the CPU.
 IO is any device that can connect to 3-
bus
 Examples:
 Interrupt controller, Timer, Keyboard
controller, mouse, LCD, lamp, LED
 communication controller, Ethernet
23 CPU-IO Communication
 CPU-IO Communication
24

 Transfer of data between IO device and CPU

 Program-controlled IO (Programmed IO, PIO, IO
Interface)
 Buffered-IO
 DMA (direct memory access) - Configurable
 Channel IO (IO Processor, IOP) - Programmable
 IO Address mapping
 Register-mapped IO
 Port-mapped IO (IO mapped IO, isolated IO)
 Memory-mapped IO
 Synchronization of the data transfer
 Polling (status checking)
 Interrupt
 Strategies for I/O (I/O
25
mechanisms)
 Programmed I/O (PIO)
 Buffered I/O
 Direct Memory Access (DMA)
 Channel I/O (IOP)
 Programmed IO (PIO)
26

 a method of transferring data between the Processor and

other peripheral devices connected, where instruction
running in the CPU performs an operation of data
transferring from and/or to an I/O device.
 In this case the Processor issues a command and then
waits for it to execute. Then it waits for the I/O device to
complete the request and respond. Processor needs to
keep check the status of the I/O device from time to time
(this is called Polling).
 The important thing to consider here is that processor is
way more faster than the I/O module and thus have to
wait for a long time to respond.
 Many older devices in a PC use PIO, including legacy serial
ports, legacy parallel ports when not in ECP mode, the
PS/2 keyboard and mouse ports, legacy MIDI and joystick
ports, the interval timer, and older network interfaces
 Buffered IO
27

 One approach to mitigating the mismatch in

timescales and speeds is to output data in bursts,
buffering it in fast memory on the slow device. A
First-In-First-Out (FIFO) buffer is filled quickly by the
CPU, and then slowly emptied by the peripheral
device.
 Obviously, the buffer must be bigger than the
volume of data that might be output in one burst,
but even this is not robust. To ensure no data is lost
the IO device must, at the very least, have a bit in
its device status word that indicates to the CPU
whether it is READY or NOT_READY to receive data.
 Buffered IO
28

A fast FIFO data buffer

 Direct Memory Access
29
(DMA)
 In DMA, data is transferred directly
between I/O module and memory. The
processor sends a request regarding
data transfer to DMA module and is
interrupted only after the entire block
has been transferred.
 Channel IO (IO Processor,
30
IOP)
 a simple, separate, independent, low-cost processor, but
self-contained, with minimal logic and sufficient on-board
scratchpad memory (working storage) to handle I/O tasks.
Typically, this processor is not powerful or flexible enough
to be used as a computer on their own and can be
construed as a form of coprocessor.
 A CPU sends relatively small channel programs to the
coprocessor via the channel to handle I/O tasks, which the
processor can, in many cases, complete without further
intervention from the CPU.
 When I/O transfer is complete or an error is detected, the
controller communicates with the CPU through the channel
using an interrupt. The channel has direct access to the
main memory, but DMA relates to non-programmable
devices.
31 IO Address Mapping
 IO Address Mapping
32

 Three sub-methods:
 Register-mapped I/O
 Port-mapped I/O (IO mapped IO)
 Memory mapped I/O
 Very similar, but that Port-mapped I/O is
more suited to microcontrollers.
 Port-Mapped IO
33

Port-mapped I/O registers can sit on the

main buses, but there must be a control
level (e.g. IO/M) that determines whether
to use main memory or the ports

IO/M
 Port-Mapped IO
34

Port address space with 212 locations 0 to

FFF in hex
 Port-Mapped IO
35

 I/O has different address bus and timing

than memory, and hence is mapped
differently. RD/WR => IOR/IOW.
 I/O has only two commands from the
CPU (IO-Read, IO-write), while memory
devices can have the full range of
commands available.
 Port-Mapped IO Design
36

 Use only input/output commands

 Input – fetch data from I/O and feed the
accumulator
 Output – Take the accumulator’s output
 Connect control signals IOR/IOW.
 Use IO/M control signal as selector to
address space.
 Port-Mapped IO – Examples
37

 Port-mapped I/O devices, which are

mapped starting address 0x20 with only
4 registers.
A5
 0x20 = 0b0010_0000

 If I/O device is the only device:

 If there’s another device in 0x60:
 Memory-Mapped IO
38

 it unlikely that the entire memory

address space is filled with physical main
memory. We could do away with the
selector IO/M if we put the I/O Registers
into available gaps in the memory
address space.
 As earlier, dual-ported registers are
required, but now writing and reading to
a device uses the standard instruction
for loading from and storing into
memory.
 Memory-Mapped IO
39

(a) IO-memory is in the memory address space. The

physical layout in (b) indicates that IO memory and
main memory are physically distinct, and plug
separately into the address and data buses
 Memory-Mapped IO
40

 Bus between CPU and memory and

between I/O devices is shared
 I/O is treated by CPU as a memory
device, and hence a memory address
space is allocated to the device
 Memory vs. Port Mapped IO
41

 Both methods have a mix of memory and I/O

registers on the same bus — but port-mapped
seems to have the disadvantage of requiring extra
control wires.
 So why is port-mapping used, particularly in
microcontrollers? There are two main reasons:
 Microcontrollers typically have a relatively small
address space. This can rather easily be filled with
physical main memory, leaving no room for I/O
registers.
 More crucial is the cost of decoding. In port-mapped
I/O only the port address lines require decoding,
whereas in memory-mapped I/O all the main-
memory’s address lines require decoding.
42
Synchronization of data
transfer
 Scheduling I/O
43

 Handshaking at different timescales

using the control bus - We cannot
reasonably use that fine-scale
handshaking to cope with
communication between the CPU and
devices which may be many orders of
magnitude slower.
 Several methods for scheduling I/O:
 Polling
 Interrupt-driven
 Polling
44

 Polling is a simple, but

often simplistic, software
solution to determine
whether a device is ready
to receive (or transmit)
data.
 The CPU regularly check
the status of the device by
reading the status bit (or
word, if there are several
bits).
 Polling - Mitigation
45

 One way of mitigating the gross

waste is to attempt to do
something useful between polls.
 However, this relies on the
program (and hence
programmer) ensuring that a
device is checked sufficiently
often.
 Hard in a system where the
various useful tasks take different
times, and where there are
several devices with differing I/O
rates
An attempt to poll while
getting on with other useful
 Interrupt-Driven IO
46

 In case of interrupt-driven I/O, processor after

requesting the I/O module proceeds with its normal
work. After I/O device has completed the request, it
notifies the processor using an interrupt.
 This relieves the processor from checking again and
again whether I/O device has completed the request.
 But, this is not very effective technique when doing it
word by word, especially when data needs to be
transferred in large quantity.
 Interrupt-Driven IO
47

 The peripheral literally interrupts the processor

from its usual grind through the programmed
instructions
 Elsewhere and already resident in the program
memory are a set of interrupt service subroutines,
each of which contains the instructions to handle a
particular sort of interrupt.
 When the interrupt is detected (on the interrupt
request (IRQ) control line), the processor stops
executing its currently programmed instructions,
jumps to execute the appropriate subroutine and,
once completed, returns to carry on with the
programmed instructions.
 Interrupt-Driven IO
48

 There are various things that need to be done

when an interrupt is received:
 Finish executing the current instruction.
 "Recognize" the interrupt. Ie, determine which
service routine is needed.
 Save all the CPU register contents (PC, Registers,
and Status Word) in memory. The Stack memory
is used for this.
 Jump to the routine, execute it, and return.
 Restore the PC, registers and status word from
the stack.
 Continue with original program sequence, as if
nothing had happened.
 Interrupt-Driven IO
49

 This is mostly like jumping to a standard

subroutine. However, as this is a routine which
could be called at anytime and hence anywhere,
there are no parameters to be passed.
 In addition, notice that the registers and status
word are saved. When a programmer writes a
subroutine, it is assumed that s/he will write it so
that data being worked on is not lost. However, an
interrupt routine is not called by the programmer,
but by the machine, and can occur at any time.
The machine must make sure the CPU’s state can
be fully restored after the interrupt.
50 I/O Processor (IOP)
 I/O Processor (I/O
51
Controller)
 The I/O Processor controls all I/O in the
system
 Both I/O processor and CPU operate in
parallel
 System throughput is enhanced
 Instruction set tailored for I/O functions
 I/O Processor Data Transfer
52

 Data transfer can be either DMA-based

or Program-controlled (Programmed IO).
 Sometimes, a single DMA is used for all
IO devices.
 IO channel or IO processor is a simple
specific controller containing DMA, with
limited set of instruction set targeting IO
applications.
 2 Channels in 8089, i.e. 2 DMA processors.
 Operation Methods
53

 Multiplexer channel
 Selector channel
 Block-multiplexer channel
 Multiplexer Channel
54

 Slow devices
 IOP can transfer data much faster than
each IO devices, and hence IO devices
are multiplexed
 Each devices is handled via a sub-
channel, usually with a dedicated
hardware
 Devices’ parameters are saved in
memory, and fetched each sub-channel
transfer
 Multiplexer Channel –
55
Modes of Operation
 Byte-interval
 Operation is divided into short intervals. In
each interval, a single IO device is served
 Transfer of 1 byte each interval (data,
status, control)
 Device is connected to IOP only for the
transaction period (~100us)
 Burst
 Device is connected till all transactions with
the current device are done
 Hard switching if transactions take too long
 Selector Channel
56

 Fast devices (e.g. Hard Disk)

 Requires a dedicated channel (similar to
multiplexer-burst operation)
 While connected, IOP cannot handle any
other task
 Block-Multiplexer Channel
57

 Combination of the former two methods

 Multiplexing of fast devices (block-by-
block transactions)
 For example:
 When handling hard disk, there are 3
commands: seek (moving the head to a
specific track), search (finding a specific
record in track), and start (read data in
record)
 Seek and search have mechanical latency.
In selector channel, channels waits. Here,
it can handle other devices till hard disk
 Representative system
58
containing an I/O Processor
59 Examples for Inputs
 Examples of Inputs
60

 Simple Digital Input

 A/D device which interfaces directly with
the micro-processor
 A/D device which DOES NOT interfaces
directly with the micro-processor
 General IO
 Keys
 4x4 Matrix Keyboard
 A/D device which interfaces
directly with the micro-
61
processor
 Contains:
 Address and Data busses to select and read/write the
registers in the I/O device
 Interrupt (EOC)/Start – to control the read/write
 CS
 Read procedure:
 “Start” to indicate the beginning of a read cycle
 After conversion-time, data is ready, and IO devices
interrupts the CPU thru EOC
 A/D device which DOES NOT
interfaces directly with the micro-
62 processor
 IO device without CS support needs
another interface to be in-between the
CPU and the IO
 Read procedure:
 IO device receives “start” from port #0
 Fetches the data and send it to the latch.
In parallel, sends EOC as interrupt to the
CPU.
 CPU reads the data from the latch, using
CS.
 Keys
63

 Keys can be:

 Switch
 Temporal
 Issue:
 “Bouncing” when keys are
pressed.
hold
 Takes time to stabilize –
might assert few interrupts
 Solution:
interface
 De-bouncer (by SW or HW)
 4x4 Matrix Keyboard -
64
Design
 Two options:
 Port A 8b are used for input,
Port B 8b are used for
output
 Port C (4b input, 4b output)
 Pressing “0” enables
readout from that
column/row.
 4x4 Matrix Keyboard -
65
Testing
 “Running zero”
 Step 1: Writing to port B, and testing
which one was pressed. Whatever
was pressed the “zero” will close
circuit to GND.
 Step 2: If “zero” was received in one
of the rows, output “zero” in the
relevant port A
66 Examples for Outputs
 Examples of Outputs
67

 Simple Digital Output

 LCD
 LED / Lamp
 Step Motor
 LCD
68

 WR
 WR data – what is going to be presented
 WR command – erase screen/ which screen to use
 Usually, have 2 types of registers, controlled by RS
 RD – status register (where applicable)
 Size of address bus depends on the number of
registers supported.
 LED / Lamp
69

 Simple light emitting

device:
 Issue - Current requested
by device might be
different than the one
provided
 Solution – driver
conversion device
 Step motor (e.g. elevator)
70

 Using few ports to control

Half step
coils One port is
 For example: used concurrently
 4 ports controlling 4 coils
 Half step – 0.9deg; Full step –
1.8deg
 Roll speed is determined by
the pace in which states are
interchanged.
Full step
 Direction is determined by the
Two ports are
choice of the state (up / down).used concurrently
 Probably, would require
current conversion.
71 Intel 8255 I/O Interface
 Minimum-mode 8086
72
system I/O interface

8255
Intel 8255 Input / Output
Interface Circuit
 I/O devices: Keyboard, Printer, Mouse, and more
 Functions of interface circuit:
 Select the I/O port

 Latch output data

 Sample input data

 Synchronize data transfer

 Translate between TTL voltage levels and those

required to operate the I/O devices

 There are 24 I/O pins which may be individually
programmed in 2 groups of 12 and used in 3
major modes of operation (basic, strobed,
bidirectional)
 8255 Functional Diagram
74
 8086 Input Bus Cycle
75
 8086 Output Bus Cycle
76
8086 IO Data Instructions
 Byte transfers involve the AL register,
and word transfers the AX Register.
78 Intel 8089 I/O Controller
 8089 IOP
79

 The 8089 is a one-chip IOP designed for use in systems

based on the 8086.
 It contains a pair of “DMA channels”, each of which can
control an independent IO operation. In addition to the
usual address and data-count registers found in DMA
controllers, the 8089’s DMA channels have their own
program counters and other circuits necessary to execute
an instruction-set that is specialized toward IO operations
 Thus, the 8089 can execute two unrelated IO programs
concurrently, and logically appears to the CPU like two
independent IOP-s.
 The DMA channels share a 20b-ALU intended mainly for
processing memory addresses. They also share the
interface circuitry for communication with main memory
and IO
 Intel 8089 IO Processor -
80
Features
 Two independent channels
 1MB system space, 64KB IO space
 Two logical buses can be treated as 8 or
16 or both to match peripherals to
system
 Channel program store can be on system
or local bus
 Instruction set tailored for IO functions
 IO - Summary
81

 There are many types of IO devices.

 There are many mechanisms for IO. The
slower ones are using programmed IO
with polling, while the faster ones are
using DMA with interrupts. A
programmable DMA is called IOP (IO
Processor).
 An example of an IO Interface is the
Intel’s 8255. An example of an IOP is the
Intel’s 8089.
82 End of lecture 3
 References
83

 Microcontroller Systems, David

Murray, 2014
 Intel 8254 datasheet, 2003
 Intel 8255 datasheet, 2006
 Intel 8089 datasheet, 1980
 Intel 8086 datasheet, 1990
 DCS Lecture Notes of Shlomo
Greenberg,
Yaara Ben-Or, 2013