ARM PROCESSORS,

INSTRUCTION SET
Unit 1 – Topic 3
 Computer Architecture Taxonomy
• The computing system consists of a central processing unit (CPU) and a
memory.
• The memory holds both data and instructions, and can be read or written
when given an address.
• A computer whose memory holds both data and instructions is known as a von
Neumann machine.
• The CPU has several internal registers that store values used internally. One of
those registers is the program counter (PC),which holds the address in
memory of an instruction.
• The CPU fetches the instruction from memory, decodes the instruction, and
executes it. The program counter does not directly determine what the
machine does next, but only indirectly by pointing to an instruction in memory.
• Harvard machine has separate memories for data and program.
• The program counter points to program memory, not data memory.
• It is harder to write self-modifying programs (programs that write data values,
then use those values as instructions) on Harvard machines.
Computer Architecture
Taxonomy
 CISC VS RISC
• Complex instruction set computers (CISC).
• These machines provided a variety of instructions that perform very
complex tasks, such as string searching; they also generally used a number
of different instruction formats of varying lengths.
• One of the advances in the development of high-performance
microprocessors was the concept of reduced instruction set computers
(RISC).
• These computers tended to provide somewhat fewer and simpler
instructions.
• The instructions were also chosen so that they could be efficiently
executed in pipelined processors. Early RISC designs substantially
outperformed
 CISC VS RISC
• Instructions can have a variety of characteristics, including:
 Fixed versus variable length.
 Addressing modes.
 Numbers of operands.
 Types of operations supported.
 Assembly Language
• Figure - A fragment of ARM assembly code to remind us of the basic
features of assembly languages.
• One instruction appears per line.
• Labels, which give names to memory locations, start in the first column.
• Instructions must start in the second column or after to distinguish them
from labels.
• Comments run from some designated comment character (; in the case of
ARM) to the end of the line.
Assembly Language
 ARM Processor
• ARM - family of RISC architectures that have been developed over many years.
• ARM - licenses its architecture to companies who either manufacture the CPU
or integrate the ARM processor into a larger system.
• Different versions of the ARM architecture are identified by different numbers.
ARM7 is a von Neumann architecture machine, ARM9 uses a Harvard
architecture.
• The textual description of instructions - an assembly language.
• ARM instructions are written one per line starting after the first column.
• Comments begin with a semicolon and continue to the end of the line.
• A label - gives a name to a memory location - at the beginning of the line,
starting in the first column.
Example:
LDR r0,[r8]; a comment
label ADD r4,r0,r1
 Processor and Memory Organization
• The ARM architecture supports two basic types of data:
 The standard ARM word is 32 bits long.
 The word - divided into four 8-bit bytes.
• ARM7 allows addresses up to 32 bits long. An address refers to a byte, not
a word.
• The word 0 in the ARM address space is at location 0, the word 1 is at 4,
the word 2 is at 8,and so on.
• The ARM processor can be configured at power-up to address the bytes in
a word in either little-endian mode (with the lowest-order byte residing
in the low-order bits of the word) or big-endian mode (the lowest-order
byte stored in the highest bits of the word), as illustrated in Figure 2.6
Processor and Memory
Organization
 Data Operations
• Figure: shows a sample fragment of C code with data declarations and
several assignment statements.
• The variables a, b, c, x, y, and z all become data locations in memory.
 Data Operations
• ARM has 16 general-purpose registers, r0 through
r15.
• The r15 register has the same capabilities as the
other registers, but it is also used as the program
counter.
• The other important basic register in the
programming model is the current program status
register (CPSR). This register is set automatically
during every arithmetic, logical, or shifting
operation.
• The top four bits of the CPSR hold the information
about the results of that arithmetic/logical
operation:
• The negative (N) bit is set when the result is negative in
two’s-complement arithmetic.
• The zero (Z) bit is set when every bit of the result is zero.
• The carry (C) bit is set when there is a carry out of the
operation.
• The overflow(V) bit is set when an arithmetic operation
results in an overflow.
DATA INSTRUCTION
Data Operations
 Flow of Control
• The B (branch) instruction is the basic mechanism in ARM for changing the
flow of control.
• The address that is the destination of the branch is often called the branch
target.
• Branches are PC-relative - the branch specifies the offset from the
current PC value to the branch target.
• The offset is in words, ARM is byte addressable, the offset is multiplied by
four (shifted left two bits, actually) to form a byte address.
• The instruction
B #100 ; will add 400 to the current PC value
Flow of Control
 ADDRESSING MODES

Immediate operands, which encode a constant value directly in the

instruction.
For example,
• Add r0,r1,#2
• Sets r0 to r1 +2.
Register-indirect addressing, the value stored in the register is used as the
address to be fetched from memory; the result of that fetch is the
desired operand value.
• Ldr r0,[r1]
Base-plus-offset addressing
• Rather than using a register value directly as an address, the register value is added to
another value to form the address.
• Ldr r0,[r1,#16]
• Loads r0 with the value stored at location r1+16. Here,r1 is referred to as the base and
the immediate value the offset.
 ADDRESSING MODES
• Auto-indexing and Post-indexing. Two variants
Auto-indexing updates the base register, such that
• LDR r0,[r1,#16]
• first adds 16 to the value of r1, and then uses that new value
as the address.
Post-indexing does not perform the offset calculation until after
the fetch has been performed.
• LDR r0,[r1],#16
• will load r0 with the value stored at the memory location
whose address is given by r1, and then add 16 to r1 and set r1
to the new value.
ADDRESSING MODES
Example: