ARCHITECTURAL

STRUCTURES AND SINGLE

PROCESSOR SYSTEM

LECTURE 9
Parallel Processing :
■ Originally, the computer has been viewed as a sequential machine.
Most computer programming languages require the programmer to
specify algorithms as sequence of instruction.
■ Processor executes programs by executing machine instructions in a
sequence and one at a time
■ By looking into these phenomenon's, researcher has to look into the
matter whether some operations can be performed in parallel or not.
■ As computer technology has evolved, and as the cost of computer
hardware has dropped, computer designers have sought more and more
opportunities for parallelism, usual to enhance performance and, in
some cases, to increase availability.
■ The taxonomy first introduced by Flynn is still the most common way of
categorizing systems with parallel processing capability. Flynn proposed
the following categories of computer system:
Flynn’s Taxonomy of computer
architecture
■ Proposed in 1966
■ General 4 category system
■ Does not clearly classify all models in use today
■ There are combinations, also.
Four Categories - Terminology
■S = Single ■SISD
■I = Instruction ■SIMD
Stream
■MISD
■M = Multiple
■MIMD
■D = Data Stream
 SISD
■Single Instruction, Single Data
stream
■ A sequential computer which exploits no parallelism in
either the instruction or data streams.
■ That is to say, one operation at a time.
■ Examples of SISD architecture are the traditional
uniprocessor machines like old personal computers.
Many had multiple cores 2010 and mainframe
SISD
SIMD
■Single Instruction, Multiple Data
streams
■ Exploits multiple data streams against a single instruction
stream to perform operations which may be naturally
parallelized.
■ Machines based on a SIMD model are well suited to
scientific computing since they involve lots of vector and
matrix operations.
■ For example, an array processor or GPU.
■ Typical for splitting large data sets.
SIMD
NOTE: Front-end processor

■ ONE processor starts the program

– It sends code to the other processors
■ In diagrams, the front-end is represented by

Instruction
Pool
which sends code to individual PU’s
PU
which execute the remaining code.
MISD
■Multiple Instruction, Single Data
stream
■ Multiple instructions operate on a single data stream.
Uncommon architecture which is generally used for fault
tolerance.
■ Machines built using the MISD model are not useful in
most of the application, a few machines are built, but
none of them are available commercially.
■ Examples include the Space Shuttle flight control
computer.
■ Least common
MISD
MIMD
■Multiple Instruction, Multiple
Data streams
■ Multiple autonomous processors simultaneously
executing different instructions on different data.
■ May send results to central location.
■ Distributed systems – can be shared memory space or
distributed memory space.
MIMD
Further divisions

Multiple instruction stream, multiple data stream (MIMD) is further

divided into two categories.
■ Single program, multiple data stream (SPMD).
Multiple autonomous processors simultaneously executing the same
program on different data. This is a common style of parallel
programming
■ Multiple programs, multiple data streams (MPMD)
Multiple autonomous processors simultaneously operating at least 2
independent programs. Such as the systems picks one node to be the
host or manager.
Alternative architectures

■ RISC (Reduced Instruction Set Computer)

■ CISC (Complex Instruction Sets computer)
SEMANTIC GAP
■ Both RISC and CISC architecture have been developed as an attempt
to cover the semantic gap.
■ With an objective of improving efficiency of software development,
several powerful programming languages have come up, viz, Ada, C+
+, and Java etc. They provide a high level of abstraction, conciseness
and power. By this evolution the semantic gap grows to enable
efficient compilation of high level language programs, CISC and RISC
designs are the two options.
■ CISC designs involve very complex architecture, including a large
number of instructions and addressing mode, whereas RISC designs
involve simplified instruction set and adapt it to the real requirement
of user programs
RISC

■ A reduced instruction set computer (RISC) is a computer that uses a

central processing unit (CPU) that implements the processor design
principle of simplified instructions. They can execute their instructions
very fast because instructions are very small and simple. It is basically
the most efficient CPU architecture technology being used to date
■ The basic concept of this architecture is to have simple instructions
that do less but execute very quickly so as to provide better
performance. In this architecture, the instructions are register based
and data transfer takes place from register to register.
RISC

■ The most basic RISC feature is a processor with a small core logic (i.e.
RISC chips require fewer transistors which make them cheaper to
design and produce), this allows engineers to increase the register set
and increase internal parallelism by using the following:
➢ Thread level parallelism: Increases the number of parallel threads
executed by the CPU.
➢ Instruction level parallelism: Increases the speed of the CPU's
executing instructions
■ In RISC, the instruction set contains simple and basic instructions from
which more complex instruction can be produced. Most instructions
complete in one cycle, which allows the processor to handle many
instructions at same time.
RISC

■ RISC processor is implemented using the hardwired control unit. The

hardwired control unit produces control signals which regulate the
working of processors hardware. RISC architecture emphasizes on
using the registers rather than memory.
■ This is because the registers are the ‘fastest’ available memory
source. The registers are physically small and are placed on the same
chip where the ALU and the control unit are placed
RISC PROCESSOR ARCHITECTURE block
diagram
RISC architecture characteristics
■ Simple instructions are used in RISC architecture.
■ RISC helps and supports few simple data types and synthesize
complex data types.
■ RISC utilizes simple addressing modes and fixed length instruction for
pipelining.
■ RISC permits any register to use in any context.
■ One cycle executing time.
■ The amount of work that a computer can perform is reduced by
separating LOAD and STORE instructions.
■ RISC contains large number of registers in order to prevent various
number of interactions with memory.
■ In RISC, pipelining is easy as the execution of all instructions will be
done in a uniform interval of time that is to say one click.
■ In RISC, more RAM is required to store assembly level instruction.
■ A compiler is used to perform the conversion operation means to
convert a high level language statement into the mode of its form.
Advantages of RISC
architecture
■ RISC architecture has asset of instruction so high level language
compilers can produce more efficient code.
■ It allows freedom of using the space on microprocessors because of
its simplicity.
■ Many RISC processors use the registers for passing arguments and
holding the local variables.
■ RISC functions use only a few parameters, and the RISC processors
cannot use the call instructions, and therefore, use a fixed length
instruction which is easy to pipeline.
■ The speed of the operation can be maximized and the execution time
can be minimized. Very less number of instructional formats, a few
numbers of instructions and a few addressing modes are needed
Disadvantages of RISC
architecture.
■ Mostly, the performance of RISC processors depends on the
programmer or compiler as the knowledge of the compiler plays a
vital role while changing the CISC code to a RISC code
■ While re arranging the CISC code to a RISC code, termed as a code
expansion, while increase the size and the quality of this code
expansion will again depend on the compiler and also on the
machines instruction set.
■ The first level cache of the RISC processor is also a disadvantage of
the RISC, in which these processors have large memory cashes on the
chip its self. For feeding the instructions, they require very fast
memory systems.
CISC
■ The CISC approach attempts to minimize the number of instructions
per program sacrificing the number of cycles per instruction.
■ Computers based on CISC architecture are deigned to decrease the
memory cost. Because the large program need more storage thus
increasing the memory cost and large memory becomes more
expensive.
■ To solve these problems the number of instructions per program can
be reduced by embedding the number of operations n a single
instruction thereby making the instruction more complex.
Characteristics of CISC
Architecture
■ Instruction decoding logic will be complex.
■ One instruction is required to support multiple addressing modes.
■ Less chip space is enough for generating purpose register for the
instructions that are operated directly on memory.
■ Various CISC designs are set up two special registers for the stack
pointer, handling interrupt.
■ MUL is referred to as complex instruction and requires the
programmer for storing functions.
Advantages of CISC
architecture.
■ Microprogramming is easy assembly language to implement and less
expensive than hard wiring a control unit.
■ The ease of micro coding new instructions allowed designers to make
CISC machines upwardly compatible.
■ As each instruction became more accomplished, fewer instructions
could be used to implement a given task.
Disadvantages of CISC
architecture
■ The performance of the machine slows down due to the amount of
clock time taken by different instruction will be dissimilar
■ Only 20% of the existing instructions is used in a typical programing
event, even though there are various specialized instructions in reality
which are not even used frequently.
■ The conditional codes are set by the CISC instructions as a side effect
of each instruction which takes time for this setting, and as the
subsequent instruction changes the conditional code bits so, the
compiler has to examine the condition code bits before this happens
RISC VS CISC
THE END