Assembly
Assembly
PROGRAMMING
MACHINE CODE INSTRUCTIONS
The only language that the CPU recognizes is machine code. Therefore, when a program
is running and an instruction is fetched from memory this has to be in the format of a
binary code that matches the specific machine code that the CPU uses.
Machine code also called machine language or object code or first generation language
Machine code is defined as low level language that can be understood directly by the
computer’s CPU.
MACHINE CODE
INSTRUCTIONS(Cont…)
An instruction may not have an operand but up to three operands are possible.
Operand defines any data needed by the instruction.
Different processors will have comparable instructions for the same operations, but
the coding of the instructions will be different.
ADVANTAGES OF MACHINE CODE
It is limited to one machine. Even if two different processors have the same instruction, the
machine codes for them will be different but the structure of the code for an instruction will
be similar for different processors.
The following must be defined for each individual machine code instruction:
Whether the opcode occupies the most significant or the least significant bits.
THE COMPONENTS OF MACHINE
CODE INSTRUCTION (CONT…)
Machine code instruction: a binary code with a defined number of bits that comprises
an opcode and, most often, one operand
OPCODE
This has an eight-bit opcode consisting of four bits for the
operation, two bits for the address mode and the remaining two
bits for addressing registers. This allows 16 different operations
each with one of four addressing modes.
The first three items on this list are there to directly assist the
programmer in writing the program . Of these, comments are
removed by the assembler and symbolic names and labels require
a conversion to binary code by the assembler. A macro is a
sequence of instructions that is to be used more than once in a
program.
FEATURES IN ASSEMBLY LANGUAGE
(CONT…)
For the absolute address example there are again no labels for
the code. The left-hand column is again just for illustration
but this time identifying actual memory addresses. This has
been coded with the understanding that the first instruction in the
program is to be stored at memory address 200.
THE ASSEMBLY PROCESS FOR A TWO-PASS
ASSEMBLER
Removal of comments
Symbol table
THE ASSEMBLY PROCESS FOR A TWO-PASS
ASSEMBLER(Cont…)
For the second pass the assembler uses the symbol table
and a lookup table that contains the binary code for each
opcode. The output of from the second pass will be a
machine code program.
THE ASSEMBLY PROCESS FOR A TWO-PASS
ASSEMBLER(Cont…)
The machine code has been coded with the first instruction
occupying address zero.
Addressing
Addressing mode
mode Use of the operand
Immediate The operand is the value to be used in the
instruction SUB #48 is an example
Direct The operand is the address which holds the value to
be used in the instruction. ADD TOTAL is an
example
Indirect The operand is an address that holds the address
which has the value to be used in the instruction
Indexed The operand is an address to which must be added
the value currently in the index register (IX) to get
address which holds the value to be used in the
ADDRESSING MODE (CONT…)
For immediate addressing there are three options for defining the
value
#48 specifies the denary value 48
#B00110000 specifies the binary equivalent
#&30 specifies the hexadecimal equivalent
ASSEMBLY LANGUAGE
INSTRUCTIONS
Data movement
These types of instruction can involve loading data into a register or storing data in
memory.
Instruction Instruction Explanation
opcode operand
LDM #n Immediate addressing load the number n to ACC
LDR #n Immediate addressing load the number n to IX
LDD <Address> Direct addressing load the contents at the given address
to ACC
LDI <Address> Indirect addressing. The address to be used is at the
given address. Load the contents of this second address
to ACC
LDX <Address> Indexed addressing. Form the address from <address>+
the contents of the index register. Copy the contents of
this calculated address to ACC.
MOV <Register> Move the contents of the accumulator to the register
ASSEMBLY LANGUAGE INSTRUCTIONS
(CONT…)
Example
ASSEMBLY LANGUAGE INSTRUCTIONS
(CONT…)
The following shows some examples of the effect of an instruction or a sequence
of instructions based on the memory content shown in above figure
LDI 106 The value 208 from address 101 is loaded into the
accumulator
instruction begins by checking whether or not the flag bit has been set.
This jump instruction does not cause an immediate jump. This is because a
new value has to be supplied to the program counter so that the next
instruction is fetched from this newly specified address. The incrementing
of the program counter that took place automatically when instruction was
fetched is overwritten.
ASSEMBLY LANGUAGE
INSTRUCTIONS (CONT…)
Arithmetic operations
Instruction Instruction Explanation
opcode operand
ADD <Address> Add the contents of the given address to the ACC
The first tree instructions initialize the count and the sum
Instructions 109 and 110 checks to see if the sum has reached
75 and if it has not the program begins the next iteration of the
loop.
Instructions 111 to 113 are only used when the sum has reached
75 which causes the value 15 stored for the count to be output.
ASSEMBLY LANGUAGE INSTRUCTIONS
(CONT…)
SHIFT OPERATIONS
There are two shift instructions available
LSL #n
Where the bits in the accumulator are shifted logically n places to the
left
LSR #n
Where the bits are shifted to the right.
Logical shift where bits in the accumulator are shifted to the right or to
the left and a zero moves into the bit position vacated.
ASSEMBLY LANGUAGE INSTRUCTIONS
(CONT…)
Cyclic shift is similar to a logical shift but bits shifted from one end
reappear at the other end
The instruction is in the CIR and only the 16-bit address needs to
be examined to identify the location of the data in memory. The
contents of that location are transferred into the accumulator.
FURTHER CONSIDERATION OF ASSEMBLY
LANGUAGE INSTRUCTIONS(Cont…)
COMPUTER ARITHMETIC
01000010
+ 01000100
-----------------------
10000110
FURTHER CONSIDERATION OF ASSEMBLY
LANGUAGE INSTRUCTIONS(Cont…)
Flags: N V C
11 0
For this example the trace table needs a column for the
accumulator, two for memory locations and one for the output.
100 IN
101 STO 200
102 IN
103 STO 201
104 IN
105 ADD 200
106 STO 200
107 ADD 201
108 INC ACC
109 OUT
110 END
FURTHER CONSIDERATION OF ASSEMBLY
LANGUAGE INSTRUCTIONS(Cont…)
The following table shows part of the instruction set for a processor. The processor has
one general purpose register, the Accumulator (ACC) and an Index Register (IX).
Exercises(Cont…)
Exercises(Cont…)
Exercises(Cont…)