PROCESSOR

FUNDAMENTAL
 THE VON NEUMANN MODEL OF A
COMPUTER SYSTEM
The model has the following basic features:
• There is a processor, a central processing unit.
• The processor has direct access to a memory.
• The memory contains a 'stored program' (which can be replaced by
another at any time)and the data required by the program.
• The stored program consists of individual instructions.
• The processor executes instructions sequentially.
CENTRAL PROCESSING UNIT (CPU)
ARCHITECTURE
COMPONENTS OF THE CPU

The three major components of CPU are:

• Arithmetic Logic Unit (ALU)
• Control Unit (CU)
• Registers
ALITHMETIC LOGIC UNIT(ALU)

The ALU is responsible for any arithmetic or logic processing that might
be needed when a program is running.
Arithmetic Logic Unit performs arithmetic computations and logical
operations.
The arithmetic computations include addition, subtraction, multiplication
and division.
The logical operations involve comparisons asking the computer to
determine if two numbers are equal or if one number is greater than or
less than another number.
THE CONTROL UNIT (CU)

Control Unit is controlling the flow of data throughout the processor and,
indeed, throughout the whole computer system . Another is ensuring that
program instructions are handled correctly.
Control Unit controls the operations of each subsystem and coordinates all
of the processor’s activities.
A vital part of the control unit is a clock which is used by the unit to
synchronize processes. There are two clocks. The first is an internal clock
which controls the cycles of activity within the processor. The other is the
system clock which controls activities outside the processor.
REGISTERS

The other components of the CPU are the registers. These are storage
components which,
because of their proximity to the ALU, allow very short access times. Each
register has limited storage capacity, typically 16, 32 or 64 bits. A register is
either general purpose or special purpose.
Accumulator: a general-purpose register that stores a value before and
after the execution of an instruction by the ALU
Registers are faster stand alone storage locations that hold data temporary.
REGISTERS (CONT…)

The full names of the special-purpose registers included in the simple

CPU
REGISTERS (CONT…)

Memory Data Register(MDR) or Memory Buffer Register(MBR)

contains the data to be stored in the computer storage (e.g.
RAM), or the data after a fetch from the computer storage. MDR
contains the data to be written into or readout of the addressed
location. act as a buffer because transfers of data within the processor
take place much more quickly than transfers outside the processor.
REGISTERS (CONT…)

Memory Address Register (MAR) This register is used to access

data and instructions from memory during the execution phase of an
instruction. Suppose CPU wants to store some data in the
memory or to read the data from the memory. It places the
address of the-required memory location in the MAR.
REGISTERS (CONT…)

The program counter (PC) it holds the address of the memory

location of the next instruction when the current instruction is
executed by the microprocessor. Stores the address of where the
next instruction is to be read from.
Index Register (IR) holds a number that can be added to (or, in some
cases, subtracted from) the address portion of a computer instruction
to form an effective address. Also known as base register. An index
register in a computer's CPU is a processor register used for modifying
operand addresses during the run of a program.
REGISTERS (CONT…)

• STATUS REGISTER (SR) is used when an instruction requires

arithmetic or logic processing. Each individual bit in the SR operates as
a flag. The bit is set to 1 if a condition is detected. As an example, the
use of the following three flags will be illustrated:
• The carry flag, identified as C, is set to 1 if there is a carry.
• The negative flag, identified as N, is set to 1 if a result is negative.
• The overflow flag, identified as V, is set to 1 if overflow is detected_
EXAMPLES
THE SYSTEM BUS

A bus is a parallel transmission component with each separate wire

carrying a single bit. A bus does not hold data. Instead, it is a
mechanism for data to be transferred from one system component to
another.
The system bus allows data flow between the CPU, the memory, and
input or output (1/0) devices
TYPES OF SYSTEM BUS

There are three types of System Bus:

The Address Bus
The Data Bus
The Control Bus
THE ADDRESS BUS

• The address bus is connected to the MAR

• Address bus: a component that carries an address to the memory
controller to identify a location in memory which is to be read from or
written to.
• The address specifies a location in memory which is due to receive data
or from which data is to be read. The address bus is a 'one-way street'. It
can only be used to send an address to a memory controller. It cannot be
used to carry an address from the memory controller back to the CPU.
THE DATA BUS

• The data bus is connected to the MDR

• Data bus: a component that carries data to and from the processor
• Word: a small number of bytes handled as a unit by the computer
system
THE CONTROL BUS

• The control bus is another bidirectional bus which transmits a signal

from the control unit to any other system component or transmits a
signal to the control unit.
• A major use of the control bus is to carry timing signals.
• The control bus is connected to the control unit
• Each 1/0 device is connected to an interface called a port. Each port is
connected to the 1/0 or device controller. This controller handles the
interaction between the CPU and an 1/0 device.
 FACTORS CONTRIBUTING TO SYSTEM
PERFORMANCE
• The processor clock speed could is a very important factor governing the processing
speed of the system.
• Modern processors are more complex. The CPU chip or integrated circuit is multi core.
Each core is a separate processor. Performance improves with increasing number of
cores.
• Performance improves with increased storage size for the cache memory and
increased rate of access.
• Bus width is again an important factor in considering how the data bus is used.

Word is a small number of bytes that can be handled as a unit by the computer system.
I/O PORTS

Each I/O device is connected to an interface called a port. Each port is

connected to the I/O or device controller. This controller handles the
interaction between the CPU and an I/O device. A port is described as
internal if the connected I/O device is an integral part of the computer
system. An external port allows the computer user to connect a
peripheral I/O device.
THE UNIVERSAL SERIAL BUS (USB)

Universal Serial Bus can be used to connect up to 127 peripheral

devices. USB supports plug and play. Plug and Play is the ability of a
computer system to automatically configure expansion boards and other
devices. So that any computer user could connect a peripheral and start
using it straight away. Nowadays anyone buying a new peripheral device
will expect it to connect to a USB port.
SPECIALISED MULTIMEDIA PORTS

The connection of the second screen can be through a Video Graphics

Array( VGA) port. This provides high resolution screen display which is
suitable for most display requirements. However, if the screen is needed
to display a video, the VGA port is not suitable because it does not
transmit the audio component.
A high Definition Multimedia Interface (HDMI) will provide a connection
to a screen and allow the transmission of high- quality video including
the audio component.
THE FETCH – EXECUTE CYCLE

The Computer uses machine cycle. A cycle is made of three phases:

Fetch
Decode
Execute
THE FETCH – EXECUTE CYCLE (CONT…)

1) Fetch: The Fetch Operation is used for taking the

instructions those are given by the user and the Instructions
those are stored into the Main Memory will be fetch by using
Registers.
THE FETCH – EXECUTE CYCLE (CONT…)

In the fetch stage, the following steps happen:

1 This address in the program counter is transferred
within the CPU to the MAR.
2 During the next clock cycle two things happen
simultaneously: the instruction held in the address pointed
to by the MAR is fetched into the MDR the address stored in
the program counter is incremented.
THE FETCH – EXECUTE CYCLE (CONT…)

3 The instruction stored in the MDR is transferred within the

CPU to the CIR.
There are two points to note here
• The clock cycle is the one controlled by the system clock
which will have settings that allow one data transfer from
memory to take place in the time defined for one cycle.
THE FETCH – EXECUTE CYCLE (CONT…)

In the final step the program counter is incremented by 1.

However, the instruction just loaded might be a jump
instruction. In this case, the program counter contents will
have to be updated in accordance with the jump condition.
This can only happen after the instruction has been decoded.
THE FETCH – EXECUTE CYCLE (CONT…)

2) Decode: The Decode Operation is used for interpreting the

Instructions means the Instructions are decoded means the CPU will
find out which Operation is to be performed on the Instructions. The
instruction stored in the CIR is received as input by the circuitry
within the control unit. Depending on the type of instruction, the
control unit will send signals to the appropriate components so that
the execution stage can begin. At this stage ALU will be activated if
the instruction requires arithmetic or logic processing.
THE FETCH – EXECUTE CYCLE (CONT…)

3) Execute: The Execute Operation is performed by the

CPU. And Results those are produced by the CPU are then
Stored into the Memory and after that they are displayed on
the user Screen.
THE FETCH – EXECUTE CYCLE (CONT…)
REGISTER TRANSFER NOTATION
REGISTER TRANSFER NOTATION
(CONT…)
• To the right of the arrow showing the transmission of data
is the definition of this data.
• The square brackets around a register abbreviation show
that the content of the register is being moved possibly
with some arithmetic operation being applied.
REGISTER TRANSFER NOTATION
(CONT…)
• When two data operations are placed on the same line
separated by a semi-colon this means that the two
transfers take place simultaneously.
• The double pair of brackets around MAR needs careful
interpretation. The content of the MAR is an address; it is
the content of that address which is being transferred to
the MDR.
INTERRUPT HANDLING

There are many different reasons for an interrupt to be

generated. Some examples are:
• A fatal error in a program
• A hardware fault
• A need for 1/0 processing to begin
• User interaction
• A timer signal.
INTERRUPT HANDLING CONT…

• The processor must have a means of identifying the type of

interrupt. One way is to have an interrupt register in the CPU that
works like the status register
• The existence of an interrupt is only detected at the end of a fetch-
execute cycle. This allows the current program to be interrupted and
left in a defined state which can be returned to later. The first step in
handling the interrupt is to store the contents of the program counter
and any other registers somewhere safe in memory.
INTERRUPT HANDLING CONT…

Following this, the appropriate interrupt handler or interrupt

service routine (ISR) program is initiated by loading its start
address into the program counter. When the ISR program has
been executed there needs to be an immediate check to see
if further interrupts need handling. If there are none, the
safely stored contents of the registers are restored to the
CPU and the originally running program is resumed.