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MPS W7-L3 Programming AVR Interrupts II

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4 views

MPS W7-L3 Programming AVR Interrupts II

Uploaded by

hussainpolyu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE-222 Microprocessor Systems

AVR Timer Interrupts


Week7-Lecture3

Dr. Sara Shakil Qureshi


Programming Timer
Interrupts
Create A Square Wave with Timer: Polling
Method
• The AVR CPU is busy for monitoring TF0!
CPU
Set Timer0 Mode and
Initial Count

If TOV0=1 NO

YES
EOR R17,R16
Timer 0 roll over
OUT PORTx,R17 TCNT0 TOV0

House-keeping
Create A Square with Timer
Interrupt
CPU Interrupt Control
Enable Interrupt

Set Timer0 Mode and


Initial Count NO
If TOV0=1

YES
Regular Work
ISR An Interrupt Event

EOR R17,R16
Timer 0 roll over
OUT
PORTx,R17 TCNT0 TOV0

RETI
Interrupt Example
• Assume that PORTC is connected to 8
switches and PORTD to 8 LEDS:
▫ Use Timer0 to generate a square wave on
PORTB.5
▫ While at the same time transfer data from
PORTC to PORTD

5
6

RETI performs the additional task of


setting the I flag
Why RETI instead of RET?
• Upon activation of the interrupt, the I bit
is cleared by the AVR itself to make sure
that no other interrupt can come in while
servicing the current one.

• RETI performs the additional task of


setting the I flag, indicating the service
the interrupt is over and the AVR can now
accept a new interrupt.
8

Example 10-2
What is the difference between the RET and RETI instructions?
Explain why we cannot use RET instead of RETI as the last
instruction of an ISR.
Solution:
Both perform the same actions of popping off the top bytes of
the
stack into the program counter, and making the AVR return to
where it left. However, RETI also performs the additional
task of setting the I flag, indicating that the servicing of the
interrupt is
over and the AVR now can accept a new interrupt on that pin.
If you use RET instead of RETI as that last instruction of the
interrupt service routine, you simply block any new interrupt
on that pin after the first interrupt, since the pin status
would indicate that the interrupt is still being serviced.
Interrupt Priority in AVR
Interrupt Priority
• If two interrupts are activated at the same time,
▫ Then the one with he higher priority is served
first.

• The priority of each interrupt is related to the


address of that interrupt in the interrupt vector
table.
11

External interrupt 0 has a higher priority than timer0 interrupt


Interrupt Programming in
C
13

What you need for the Interrupt


Programming in C?
1. Interrupt include file:#include <avr\interrupt.h>

2. Macros to clear and set the I-bit in


SREG: cli() and sei()

3. Defining the ISR: to write an ISR, use


the following structure
ISR (interrupt vector name)
{
your program
}
14
Example-1: C programming
• Using Timer0 generate a square wave on pin PORTB.5,
while at the same time transferring data from PORTC to
PORTD.
#include "avr/io.h"
#include "avr/interrupt.h"
int main ()
{
DDRB |= (1<<5); //DDRB.5 = output
TCNT0 = -32; //timer value for 2 µs
TCCR0 = 0x01; //Normal mode, int clk, no prescaler
TIMSK0 = (1<<TOIE0); //enable Timer0 overflow interrupt
sei (); //enable interrupts
DDRC = 0x00; //make PORTC input
DDRD = 0xFF; //make PORTD output
while (1) //wait here
PORTD = PINC;
}
ISR (TIMER0_OVF_vect) //ISR for Timer0 overflow
{
TCNT0 = -32;
PORTB ^= 0x20; //toggle PORTB.5
}

15
Programming External Hardware
Interrupts
Review: Pin-out ATmega16As

http://ww1.microchip.com/downloads/en/devicedoc/atmel-8154-8-bit-avr-
External Interrupts
• External interrupts are triggered by the:
▫ INT0
▫ INT1
▫ INT2 [only edge triggered interrupt]

• GICR Register: To enable/disable external interrupt

• Note: if external interrupt is enabled, the interrupts will


trigger even if the INT0:2 pins are configured as outputs:
▫ This provides a way of generating a Software Interrupt
Interrupt Sense Control
• The external interrupt can be triggered by a:
▫ Falling edge
▫ Rising edge
▫ Low-level

• Upon reset, INT0 and INT1 are low-level triggered


interrupts,
▫ See next slide for edge triggered configuration

• INT2 is only edge triggered interrupt.


Interrupt Sense Control for INT0
and INT1: MCUCR
Interrupt Sense Control for INT2:
MCUCSR
GIFR: General Interrupt Flag
Register
• In case of edge-triggered mode:
[Falling/Rising/Change-level]
▫ The related INTFx flag is set upon triggering
an interrupt
▫ The related INTFx flag is cleared when the
AVR jumps to corresponding ISR

▫ the interrupt pulse must last for at least 1 c.c


to ensure that the transition is seen by the AVR
GIFR: General Interrupt Flag
Register
• In case of level-triggered interrupts:
▫ The interrupt is NOT latched i.e INTFx flag
remains unchanged when an interrupt occurs
 The state of the pin is read directly

▫ Pin must be held low for a min. of 5 c.c to be


recognized.
24

Conclusion
• Programming AVR External Interrupts
▫ INT0 & INT1
▫ INT2
▫ GIFR
25

Reading Material
• Textbook:
▫ Chapter 10
26

Questions?

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