COMPUTER ORGANIZATION AND DESIGN

6
Edition
th

The Hardware/Software Interface

Chapter 5
Large and Fast: Exploiting
Memory Hierarchy
PART 1

Chapter 2 — Instructions: Language of the Computer — 2

 §5.1 Introduction
Principle of Locality
 Programs access a small proportion of
their address space at any time
 Temporal locality
 Items accessed recently are likely to be
accessed again soon
 e.g., instructions in a loop, induction variables
 Spatial locality
 Items near those accessed recently are likely
to be accessed soon
 E.g., sequential instruction access, array data
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 3
Taking Advantage of Locality
 Memory hierarchy
 Store everything on disk
 Copy recently accessed (and nearby)
items from disk to smaller DRAM memory
 Main memory
 Copy more recently accessed (and
nearby) items from DRAM to smaller
SRAM memory
 Cache memory attached to CPU

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 4

Memory Hierarchy Levels
 Block (aka line): unit of copying
 May be multiple words
 If accessed data is present in
upper level
 Hit: access satisfied by upper level

Hit ratio: hits/accesses
 If accessed data is absent
 Miss: block copied from lower level

Time taken: miss penalty

Miss ratio: misses/accesses
= 1 – hit ratio
 Then accessed data supplied from
upper level

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 5

 §5.2 Memory Technologies
Memory Technology
 Static RAM (SRAM)
 0.5ns – 2.5ns, $500 – $1000 per GB
 Dynamic RAM (DRAM)
 50ns – 70ns, $3 – $6 per GB
 Magnetic disk
 5ms – 20ms, $0.01 – $0.02 per GB
 Ideal memory
 Access time of SRAM
 Capacity and cost/GB of disk

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 6

DRAM Technology
 Data stored as a charge in a capacitor
 Single transistor used to access the charge
 Must periodically be refreshed

Read contents and write back

Performed on a DRAM “row”

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 7

 DRAM Technology-details
 Data stored as a charge in a capacitor:
 In DRAM, information is stored as an electrical charge in capacitors. Each capacitor
represents a binary bit, with the presence or absence of charge signifying 0 or 1.
 Single transistor used to access the charge:
 To read or modify the data stored in a capacitor, a single transistor is employed. The
transistor acts as a switch that controls the flow of charge to or from the capacitor.
 Must periodically be refreshed:
 Unlike Static Random-Access Memory (SRAM), which can hold data as long as power is
supplied, DRAM requires periodic refreshing. This is because the charge in the capacitors
tends to leak away over time. Refresh operations involve rewriting the data to maintain its
integrity.
 Read contents and write back:
 Reading involves determining the presence or absence of charge in a capacitor,
representing the binary state. Writing back involves modifying the charge to update the
stored data.
 Performed on a DRAM “row”:
 DRAM is organized into rows and columns. Accessing or modifying data is typically done on
an entire row of capacitors at once. This is a common practice in DRAM architecture and
helps improve efficiency in memory operations.
 In summary, DRAM uses capacitors to store data as charges, and a single transistor is employed
to access and manipulate this data. Periodic refreshing is necessary to counter charge leakage,
and operations are typically performed on entire rows of data for efficiency.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 8

 Advanced DRAM
Organization
 Bits in a DRAM are organized as a rectangular
array
 DRAM accesses an entire row
 Burst mode: supply successive words from a row with
reduced latency (Instead of accessing each piece of data individually, burst mode
enables the memory controller to retrieve a continuous sequence or "burst" of data words in a
more efficient manner)
 Double data rate (DDR) DRAM
 Transfer on rising and falling clock edges (DDR memory effectively doubles
the data transfer rate by utilizing both edges. This allows for higher data bandwidth and improved overall
performance in terms of data throughput
 Quad data rate (QDR) DRAM
 Quad Data Rate: Data is transferred on both the rising and falling edges of two different
clock signals, effectively quadrupling the data rate.
 Separate DDR Inputs and Outputs: Unlike DDR memory, which shares the same data
lines for reading and writing, QDR DRAM has separate input and output lines for faster and
more efficient data transfer
DRAM Generations
Year Capacity $/GB
1980 64 Kibibit $6,480,000
1983 256 Kibibit $1,980,000
1985 1 Mebibit $720,000
1989 4 Mebibit $128,000
1992 16 Mebibit $30,000
1996 64 Mebibit $9,000
1998 128 Mebibit $900
2000 256 Mebibit $840
2004 512 Mebibit $150
2007 1 Gibibit $40
2010 2 Gibibit $13
2012 4 Gibibit $5
2015 8 Gibibit $7
2018 16 Gibibit $6 TRAC (Total Cost of Acquisition)
TCAC (Total Cost of Acquisition and Conversion)

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 10

DRAM Performance Factors
 Row buffer
 Allows several words to be read and refreshed in
parallel
 Synchronous DRAM
 Allows for consecutive accesses in bursts without
needing to send each address (allows for faster data access
by reading or writing a sequence of contiguous memory addresses after
a single initial address is provided)
 Improves bandwidth
 DRAM banking
 Allows simultaneous access to multiple DRAMs
 Improves bandwidth
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 11
Increasing Memory Bandwidth

 4-word wide memory

 Miss penalty = 1 + 15 + 1 = 17 bus cycles
 Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle
 4-bank interleaved memory
 Miss penalty = 1 + 15 + 4×1 = 20 bus cycles
 Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 12
 Increasing Memory Bandwidth-cont
the performance characteristics of memory systems with different configurations: a 4-word wide memory
and a 4-bank interleaved memory:
4-Word Wide Memory:
1. A 4-word wide memory means that the memory system can fetch or store four words of data in a
single operation.
2. Miss Penalty Calculation:
1. The miss penalty is a measure of the cost incurred when data is not found in the cache and
needs to be fetched from the main memory. The calculation here is 1 (time to determine a
miss) + 15 (time to access the main memory) + 1 (additional time).
3. Bandwidth Calculation:
1. Bandwidth is the amount of data that can be transferred per unit of time. The calculation is
based on the fact that 16 bytes of data are transferred in 17 bus cycles. The result is 16
bytes / 17 cycles = 0.94 bytes per cycle.
Bank Interleaved Memory:
1. A 4-bank interleaved memory means that the memory is organized in a way that allows for
concurrent access to data from four different banks.
2. Miss Penalty Calculation:
1. Similar to the 4-word wide memory, the miss penalty calculation here includes 1 (time to
determine a miss) + 15 (time to access the main memory) + 4 × 1 (additional time for the
four banks).
3. Bandwidth Calculation:
1. Bandwidth is calculated based on the transfer of 16 bytes of data in 20 bus cycles. The
result is 16 bytes / 20 cycles = 0.8 bytes per cycle.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 13

Flash Storage
 Nonvolatile semiconductor storage
 100× – 1000× faster than disk
 Smaller, lower power, more robust
 But more $/GB (between disk and DRAM)

Chapter 6 — Storage and Other I/O Topics — 14

 Flash Types
 NOR flash: bit cell like a NOR gate

Suited for random access read operations.
 Faster read speeds, making it suitable for code execution.
 Used in applications like embedded systems, microcontrollers, and BIOS.
 Generally more expensive and has lower storage density.

 NAND flash: bit cell like a NAND gate

 Optimized for sequential access read and write operations.

Higher write and erase speeds, suitable for mass storage.

Widely used in USB drives, memory cards, and SSDs.
 More cost-effective for high-capacity storage solutions.

 Flash bits wears out after 1000’s of accesses

 Flash memory has a limited number of write and erase cycles, often in the thousands. With
repeated use, the memory cells can wear out, affecting data reliability over time.
 Not suitable for direct RAM or disk replacement
 Wear leveling: remap data to less used blocks (To address uneven
wear, wear leveling is employed. This technique redistributes write and erase cycles more evenly across
the memory cells by remapping data to less used blocks. It helps extend the overall lifespan of the flash
memory.)

Chapter 6 — Storage and Other I/O Topics — 15

Disk Storage
 Nonvolatile, rotating magnetic storage

Chapter 6 — Storage and Other I/O Topics — 16

Disk Sectors and Access
 Each sector records
 Sector ID
 Data (512 bytes, 4096 bytes proposed)
 Error correcting code (ECC)

Used to hide defects and recording errors
 Synchronization fields and gaps
 Access to a sector involves
 Queuing delay if other accesses are pending
 Seek: move the heads
 Rotational latency
 Data transfer
 Controller overhead

Chapter 6 — Storage and Other I/O Topics — 17

Disk Access Example
The average read time for a disk access is calculated by summing up the following four components:
Given Data:

• Sector size: 512B

• Disk speed: 15,000 RPM (Rotations Per Minute)
• Average seek time: 4ms
• Transfer rate: 100MB/s
• Controller overhead: 0.2ms
•Average Read Time=Seek Time+Rotational Latency+Transfer Time+Controller Delay

1. Seek Time:
The time taken to position the read/write head over the correct track.
Given as 4ms.
2. Rotational Latency:
Time taken for the desired sector to rotate under the read/write head.
The disk spins at 15,000 RPM, meaning:
Time per revolution=60 sec/15,000=4 ms per revolution
Time per revolution=15,00060 sec​=4 ms per revolution
On average, the desired sector will be halfway around, so:
Rotational latency=1/2×4=2 ms
3. Transfer Time:
Time to read the 512B sector.
Given the transfer rate is 100MB/s, we convert:
100MB/s=100×1024×1024 bytes per second=104,857,600 B/s
Transfer time=512/104,857,600=0.00000488 seconds=0.005 ms
4. Controller Overhead:
Delay due to processing overhead in the disk controller.
Given as 0.2ms.
Total Average Read Time:
4 ms+2 ms+0.005 ms+0.2 ms=6.2 ms
Thus, the average time required to read a sector from disk is 6.2ms.
 Disk Access Example
The average read time for a disk access is calculated by summing up the
following four components:
Sector size, Disk speed, (Rotations Per Minute), Average seek time, Transfer
rate, Controller overhead

Average Read Time=Seek Time+Rotational Latency+Transfer Time+Controller

 Given
512B sector, 15,000rpm, 4ms average seek time, 100MB/s transfer rate,


0.2ms controller overhead, idle disk

Average read time


4ms seek time
+ ½ / (15,000/60) = 2ms rotational latency
+ 512 / 100MB/s = 0.005ms transfer time
+ 0.2ms controller delay
= 6.2ms

Chapter 6 — Storage and Other I/O Topics — 19

Disk Access Example-details
 4ms seek time:
 This is the time it takes for the drive's read/write head to position itself over the
correct track. In this case, it's 4 milliseconds.
 ½ / (15,000/60) = 2ms rotational latency:
 The rotational latency is the time it takes for the desired sector to rotate under the
read/write head. For a 15,000 revolutions per minute (RPM) drive, the average
time for half a rotation (represented by ½) is calculated. Dividing by 15,000/60
converts RPM to revolutions per second. This yields the rotational latency, which
is 2 milliseconds.
 512 / 100MB/s = 0.005ms transfer time:
 This component represents the time it takes to transfer the actual data once the
correct sector is under the read/write head. The calculation divides the size of the
data transfer (512 bytes) by the data transfer rate (100 megabytes per second).
 0.2ms controller delay:
 This accounts for the time spent by the controller in managing the data transfer.
 Adding these components together:
 Average Read Time=Seek Time+Rotational Latency+Transfer Time+Controller =4 ms
+2 ms+0.005 ms+0.2 ms=6.205 ms

Chapter 6 — Storage and Other I/O Topics — 20

Disk Performance Issues
 Manufacturers quote average seek time
 Based on all possible seeks
 Locality and OS scheduling lead to smaller actual
average seek times
 Smart disk controller allocate physical sectors on
disk
 Present logical sector interface to host
 SCSI, ATA, SATA
 Disk drives include caches
 Prefetch sectors in anticipation of access
 Avoid seek and rotational delay

Chapter 6 — Storage and Other I/O Topics — 21

 §5.3 The Basics of Caches
Cache Memory
 Cache memory
 The level of the memory hierarchy closest to
the CPU
 Given accesses X1, …, Xn–1, Xn

 How do we know if
the data is present?
 Where do we look?

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 22

 §5.3 The Basics of Caches
Cache Memory -Cont
Cache memory is a type of high-speed volatile computer memory that provides high-speed data
access to a processor and stores frequently used computer programs, applications, and data. In
the memory hierarchy, cache is situated closest to the CPU, making it the fastest type of memory
available to the processor.
When a CPU needs to access data, it first checks whether the required data is present in the
cache. This process involves looking into the cache for the requested information. Here's a brief
explanation of how this is typically done:
1.Checking for Data Presence:
1. The cache memory is organized into blocks or lines, and each block contains a subset
of the data from the main memory. A cache controller manages these blocks and tracks
the data present in the cache.
2.Using Memory Addresses (X1, …, Xn–1, Xn):
1. When the CPU issues a memory access request, it comes with a specific memory
address. This address is used to identify the location of the required data.
3.Comparing Memory Addresses:
1. The cache controller compares the memory address of the requested data with the
addresses of the data stored in the cache. If there's a match, it means the required data
is present in the cache.
4.Hit or Miss:
1. If the comparison results in a match, it's called a "cache hit," indicating that the data is
already in the cache, and the CPU can directly access it. If there's no match, it's called
a "cache miss," meaning the required data is not in the cache.
5.Handling Cache Miss:
1. In the case of a cache miss, the cache controller fetches the required data from the
lower levels of the memory hierarchy (e.g., main memory or even further down) and
loads it into the cache for future access.
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 23
Direct Mapped Cache
 Location determined by address: Mapping of a block from main memory to a specific
cache location is determined directly by the address of the data.

 Direct mapped: only one choice (For a given block of data in main memory, there is only
one specific location in the cache where that block can be placed)
 (Block address) modulo (#Blocks in cache)-The block address is divided by the
total number of blocks in the cache, and the remainder (modulo) determines the cache location. This ensures that the cache
locations are distributed evenly.

 #Blocks is a power of 2
 Use low-order address bits -Utilizing
the least significant bits of the memory address for determining the
cache location. the low-order bits of the memory address are
employed to index into the cache and determine the specific cache
location where a particular block of data should be stored or
retrieved.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 24

Tags and Valid Bits
 How do we know which particular block is
stored in a cache location?
 Store block address as well as the data
 Actually, only need the high-order bits
 Called the tag
 What if there is no data in a location?
 Valid bit: 1 = present, 0 = not present
 Initially 0

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 25

 Tags and Valid Bits-details
 In a cache memory system, "Tags" and "Valid Bits" are used to manage and identify which particular
block is stored in a given cache location:
 Tags for Identification:
 To know which specific block is stored in a cache location, the block's address is stored along
with the actual data. However, instead of storing the entire address, only the high-order bits (most
significant bits) are kept. This high-order portion is called the "tag." It serves as an identifier for
the block stored in the cache.
 Storage of Block Address and Data:
 Each entry in the cache typically stores both the tag (high-order bits of the block address) and the
associated data. This pairing allows the cache to quickly identify whether the requested data is
present and, if so, retrieve it.
 Validity Check with Valid Bits:
 Valid bits are used to indicate whether a particular cache location contains valid data. The valid
bit is associated with each cache entry. If the valid bit is set to 1, it means that the data in that
cache location is valid and corresponds to a block in the main memory. If the valid bit is 0, it
indicates that the cache location is currently empty or does not contain valid data.
 Initialization with Valid Bits:
 When the cache is initially set up or when data is evicted from a cache location, the valid bit is
typically set to 0. This signifies that the cache location is not holding valid data at that point.
 The combination of tags and valid bits helps manage the cache's content and allows the system to
quickly identify whether a requested block is present in the cache. The tags provide an efficient way to
match addresses, and the valid bits indicate the current status of the data in a given cache location

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 26

Cache Example-direct mapping
 8-blocks, 1 word/block, direct mapped
 Initial state

Index V Tag Data

000 N
001 N
010 N
011 N
100 N
101 N
110 N
111 N

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 27

 Cache Example
Word addr Binary addr Hit/miss Cache block
22 10 110 Miss 110
• Initially processor will read the
address 22 on cache
Index V Tag Data
• Address of 22 in cache 22 mod 8 =
6 = 110 000 N
• 110 is N (empty) so miss
001 N
• So processor go to lower level to
the Ram, get memory of 22 : 010 N
Mem[10110] and out it in cache
• In the tag will put the upper bits:10 011 N
• So tag + index is the address of 100 N
word that we will read from
memory 101 N
• Once read the V becomes 1 or Y 110 Y 10 Mem[10110]
111 N

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 28

 Cache Example –more details
Word addr Binary addr Hit/miss Cache block
1. Processor Requests Address 22
 Binary representation of 22: 10 110
22 10 110 Miss 110
 The cache index is calculated using:
- 22 mod 8= 6 (binary: 110) Index V Tag Data
 The processor checks cache block 110.
2. Cache Miss (Data Not Found in Cache)
000 N
The cache entry at index 110 is empty (N for not valid).
001 N


 This results in a cache miss.

3. Fetching from RAM 010 N
 The processor retrieves data from main memory at address
10110 (22 in binary). 011 N
 It stores the data in cache block 110. 100 N
 The tag (upper bits: 10) is stored to identify
this data. 101 N
4. Updating Cache 110 Y 10 Mem[10110]
 The valid bit (V) is set to Y (yes), meaning the data is now in
cache.
111 N
 The tag (10) and data (Mem[10110]) are
stored in the cache.
5. Future Access to Address 22
 If the processor requests 22 again, it will find it in the cache
(cache hit), avoiding memory access delays.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 29

 Cache Example
• Initially processor will read the Word addr Binary addr Hit/miss Cache
address 26 on cache block
• Address of 22 in cache 26 mod 8 =
1 = 010 26 11 010 Miss 010
• 010 is N (empty) so miss
• So processor go to lower level to Index V Tag Data
the Ram, get memory of 22 :
Mem[11010] and out it in cache 000 N
• In the tag will put the upper bits:11 001 N
• So tag + index is the address of
word that we will read from 010 Y 11 Mem[11010]
memory 011 N
• Once read the V becomes 1 or Y
100 N
101 N
110 Y 10 Mem[10110]
111 N

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 30

 Cache Example – More details
1. Processor Requests Address 26
 Binary representation of 26: 11 010 Word addr Binar Hit/ Cache
 The cache index is determined using: y mis block
• 26mod 8=2(binary: 010) addr s
 The processor checks cache block 010. 26 11 Mis 010
2. Cache Miss (Data Not Found in Cache) 010 s
 The cache entry at index 010 is empty (N for not valid).
 This results in a cache miss. Index V Tag Data
3. Fetching from RAM
• The processor retrieves data from memory address 11010 (26 in decimal). 000 N
• It stores the data in cache block 010.
001 N
• The tag (upper bits: 11) is stored to identify this data.
4. Updating Cache 010 Y 11 Mem[110
 The valid bit (V) is set to Y (yes), meaning the data is now in cache. 10]
 The tag (11) and data (Mem[11010]) are stored in the cache. 011 N
5. Future Access to Address 26
• If the processor requests 26 again, it will find it in the cache (cache hit), avoiding
100 N
memory access delays.
101 N
Results:
 Tag: 11 (Stored in the cache to verify future accesses)
110 Y 10 Mem[1011
Index: 010 (Determines which cache block is used)

0]
 Data: Retrieved from RAM and stored in Mem[11010] 111 N
Summary : Address 26 maps to cache block 010. The tag stored is 11.The
cache misses initially, fetching data from RAM.
• After loading, any future request for 26 will result in a cache hit.
 Cache Example
Word addr Binary addr Hit/miss Cache block
22 10 110 Hit 110
26 11 010 Hit 010
Processor reads 22 in
cache (110).
Found V = Y,
Now compares the Tag Index V Tag Data
value (10) with index 110
with the address 10110 . 000 N
They match then Hit,
correct data.
001 N
So read from cache, no 010 Y 11 Mem[11010]
access to Ram
011 N
Same thig for 26 100 N
101 N
110 Y 10 Mem[10110]
111 N

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 32

 Cache Example
1. Accessing Word Address 16 (Binary: 10 000) Word addr Binary Hit/ Cache
• Binary Address: 10 000 addr miss block
• Cache Block Calculation:
16 mod 8 = 0 (Index 000) 16 10 000 Miss 000
• Cache Index 000 is Empty → Cache Miss
• The processor fetches memory at address 10000 and stores it
3 00 011 Miss 011
in cache block 000.
16 10 000 Hit 000
• Tag stored: 10 (upper bits of address).
• Valid bit (V) is set to Y, meaning this block now contains data.
2. Accessing Word Address 3 (Binary: 00 011) Index V Ta Data
• Binary Address: 00 011 g
• Cache Block Calculation: 000 Y 10 Mem[10000]
3 mod 8 = 3( Index 011)
(Data from Word
• Cache Index 011 is Empty → Cache Miss address 16)
• The processor fetches memory at address 00011 and stores it
in cache block 011. 001 N
• Tag stored: 00 (upper bits of address).
• Valid bit (V) is set to Y. 010 Y 11 Mem[11010]
3. Accessing Word Address 16 Again (Binary: 10 000)
• Binary Address: 10 000 011 Y 00 Mem[00011] (Data
from Word Address 3)
• Cache Block Calculation:
16 mod 8 = 0 (Index 000) 100 N
• Cache Index 000 contains a valid entry with Tag = 10.
• Tag Matches → Cache Hit 101 N
• The data Mem[10000] is retrieved from the cache instead of
RAM, improving performance. 110 Y 10 Mem[10110]

111 N
 Cache Example
Word Binary Hit/ Cache
Processor reads address 18 addr addr miss block
The cache index is 010 18 10 010 Miss 010
The Tag of 010 is 11 When add combine index to tag then
compare to address they don’t match so Miss
Index V Tag Data
So address of Mem[10010] Doesn't match 10010 so doesn't read
from this address just flag Miss and go read from Ram 000 Y 10 Mem[10000]

001 N

010 Y 11 Mem[11010]

011 Y 00 Mem[00011]

100 N

101 N

110 Y 10 Mem[10110]

111 N

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 34

 Cache Example -details
1. Processor Requests Address 18
 Binary representation of 18: 10 010
Word Binary Hit/ Cache
addr addr miss block
 Cache Index Calculation:
18 mod 8 = 2 (Index: 010) 18 10 010 Miss 010
 The processor checks cache block 010 for the requested data.
2. Cache Miss Occurs
Index V Tag Data
 The cache entry at Index 010 contains:
 Tag: 11 000 Y 10 Mem[10000]
 Data: Mem[11010] 001 N
 The requested memory address 18 (10 010) has a tag of
010 Y 11(old) Mem[11010]
10, but the stored tag in the cache block is 11.
(old,
 Since the tag does not match, it results in a cache miss. incorrect
3. Fetching from RAM data)
 Since Mem[11010] (stored data) does not match the 011 Y 00 Mem[00011]
requested address Mem[10010], the cache does not use
it. 100 N
 The processor retrieves data from memory address 101 N
10010 in RAM.
4. Updating the Cache 110 Y 10 Mem[10110]
 The fetched memory block Mem[10010] will replace the 111 N
current data at index 010.
 The tag is updated to 10 to match the requested
memory.
 The valid bit (V) is set to Y, meaning the block now
 Cache Example
Will then go to Ram and read Word addr Binary addr Hit/miss Cache block
the correct address 18 10 010 Miss 010
Mem[10010] and change the
tag to 10
Index V Tag Data
000 Y 10 Mem[10000]
001 N
010 Y 10 Mem[11010] Mem[10010]
011 Y 00 Mem[00011]
100 N
101 N
110 Y 10 Mem[10110]
111 N

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 36

 Address Subdivision
• A cache memory system, showing a
32-bit address divided into a 20-bit
tag, a 10-bit index, and a 2-bit byte
offset.
• The tag identifies if the data is in the
cache, the index selects the cache
line, and the byte offset locates the
specific byte within the cache line.
• A comparator checks for a cache hit
by comparing the address tag with
the cache line's tag; if they match
and the data is valid, the data is
accessed from the cache.
• Otherwise, a cache miss occurs,
requiring data retrieval from the
main memory.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 37

Example: Larger Block Size
 64 blocks, 16 bytes/block
 To what block number does address 1200 map?
 Block address = 1200/16 = 75 (because cache is divided
16 bytes per block)

 Block number = 75 modulo 64 = 11(this is wher the 1200 is

mapped to which is the value of index (the 6 bits))

Index: determines
31 10 9 4 3 0 location of the
block in the cache
Tag Index Offset
Offset: Determine
22 bits 6 bits 4 bits
location of Byte
26 24 inside the block

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 38

 Block Size Considerations
1. Larger Blocks Reduce Miss Rate

Why? Due to spatial locality, when we fetch a block, we bring more nearby data
into the cache.

Benefit: This reduces the number of times we need to go to main memory.
2. Problems with Large Blocks in a Fixed-Size Cache

Fewer Blocks in Cache: Since the cache size is fixed, larger blocks mean we
store fewer of them.

More Competition: More memory locations will compete for space, which
increases cache misses.

Cache Pollution: Large blocks might bring in unneeded data, replacing useful
data.
3. Larger Miss Penalty

Slow Fetching: When a miss happens, fetching a larger block takes more time.

Might Cancel Benefits: The time wasted on a miss might eliminate the benefit of
having fewer misses.

Solutions:

Early Restart: Start using the requested word before the full block loads.

Critical-Word-First: Load the needed word first, then fetch the rest.
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 39
 Cache Misses
1. On Cache Hit:
 If the requested data is found in the cache, the CPU continues

processing without delay.

2. On Cache Miss:
 If the data is not in the cache, the CPU must pause (stall the

pipeline) while retrieving it.

 The missing data is fetched from the next level of memory (e.g.,

RAM).
3. Types of Cache Misses:
 Instruction Cache Miss:


Happens when the CPU can't find the next instruction in the
cache.

The CPU restarts instruction fetching from memory.
 Data Cache Miss:


Happens when the required data is not in the cache.

The CPU waits until the data is fully loaded before continuing.
Types of Data Write in Cache Memory:
Data write refers to the process of storing or updating data in memory when a
program executes a store (write) instruction. This happens when the CPU wants
to write new data into a memory location, either in the cache or main memory.

Types of Data Write in Cache Memory:

1. Write Hit (Data is in Cache)

 The CPU finds the data in cache and needs to update it.
 The challenge: Should the change be only in the cache or also written to main memory?
 If only the cache is updated, memory becomes inconsistent.

2. Write-Through (Update Both Cache & Memory)

 Every write operation updates both the cache and the main memory.
 Ensures consistency but is slow because memory writes take time.

3. Write Buffer (Improves Performance)

 Instead of waiting, the CPU places data in a buffer that writes it to memory later.
 This allows the CPU to continue working immediately, reducing delays.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 41

 Write-Back
1. Write-Back (Alternative to Write-Through)
 Instead of updating both cache and memory on every write, only the cache
is updated.
 This reduces memory writes, making it faster than write-through.
2. Tracking Changes with Dirty Bits
 Each cache block has a "dirty bit" that marks if it has been modified but not
yet written to RAM.
 If dirty = 1, the block is changed in cache but not in RAM yet.
3. When a Dirty Block is Replaced
 If a dirty block is removed from cache, it must be written back to RAM
before being replaced.
 This ensures memory gets the latest data.
4. Using a Write Buffer
 A write buffer temporarily holds the dirty block while the new block is read.
 This allows the CPU to continue without waiting for the write to finish.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 42

 Write Allocation
A write miss happens when the CPU tries to write data, but the block is not found in the cache.
There are different ways to handle this:
1. Alternatives for Write-Through Cache
Allocate on Miss:

 Fetch the block from RAM, store it in the cache, and then write the new data.
 Ensures future accesses are faster but adds extra memory access time.
Write Around:
 Do NOT fetch the block into the cache, just write directly to RAM.
 Useful when programs overwrite entire blocks before reading them (e.g., initializing data).
 Avoids unnecessary cache pollution but may slow down future reads.
2. For Write-Back Cache
Usually Fetch the Block:

 The block is loaded into cache first, and then the write occurs.
 Ensures that future writes can be done quickly in cache without writing to RAM
immediately.
Summary
 Write-Through: Either fetch block on a miss (allocate on miss) or skip fetching and write only to
RAM (write around).
 Write-Back: Usually fetches the block, so future writes stay in cache before updating RAM.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 43

 Example: Intrinsity FastMATH
The Intrinsity FastMATH processor is a high-speed embedded MIPS processor with
separate instruction and data caches to improve performance. It minimizes instruction
cache misses but has a higher data cache miss rate. The D-cache supports both write-
through and write-back to manage data storage efficiently.

1. Processor Type:
It is an embedded MIPS processor optimized for performance.

Uses a 12-stage pipeline to execute instructions efficiently.

Can access both instructions and data in the same cycle for faster execution.

2. Cache Architecture:
Split cache design → Separate Instruction Cache (I-cache) and Data Cache (D-cache).

Each cache is 16KB, containing 256 blocks with 16 words per block.

D-cache supports both write-through and write-back policies for data storage.

3. Performance (SPEC2000 Benchmark Miss Rates):

I-cache miss rate: 0.4% (very efficient at fetching instructions).

D-cache miss rate: 11.4% (higher, meaning more data requests need to access main

memory).
Weighted average miss rate: 3.2%, showing overall efficiency.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 44

Example: Intrinsity FastMATH

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 45

 Main Memory Supporting Caches
1. Using DRAM for Main Memory
 The computer uses DRAM (Dynamic RAM) as main memory.

Each memory unit has a fixed width (e.g., 1 word per access).

DRAM is connected to the CPU via a clocked bus, which is slower than the CPU clock.

2. Example: Reading a Cache Block

1 bus cycle is needed to send the memory address.

15 bus cycles are required for DRAM to access the data.

1 bus cycle per word is needed to transfer data from DRAM to cache.

3. For a 4-Word Block with a 1-Word-Wide DRAM:

Miss penalty (total time to fetch a block) is:

1+(4×15)+(4×1)=65 bus cycles

 Bandwidth (speed of data transfer):

16 bytes / 65 cycles=0.25 B/cycle

This means data transfer is slow, and fetching from DRAM takes time.

Summary:
DRAM is slower than the CPU, causing delays when fetching data.

Fetching a block requires multiple bus cycles, making cache performance important.

Miss penalty is high (65 cycles), and bandwidth is low (0.25 B/cycle), meaning memory

access needs optimization.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 46

 §5.4 Measuring and Improving Cache Performance
Measuring Cache Performance
 Components of CPU time

Program execution cycles

Includes cache hit time

Memory stall cycles

Mainly from cache misses
 With simplifying assumptions:
Memory stall cycles
Memory accesses
 Miss rate Miss penalty
Program
Instructions Misses
  Miss penalty
Program Instruction
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 47
 Cache Performance Example

Miss cycles per instruction

Given I-cache: 0.02 × 100 = 2
I-cache miss rate = 2% D-cache: 0.36 × 0.04 × 100 =
D-cache miss rate = 4% 1.44
Miss penalty = 100 cycles Actual CPI = 2 + 2 + 1.44 = 5.44
Base CPI (ideal cache) = 2 Ideal CPU is 5.44/2 =2.72
Load & stores are 36% of times faster
instructions

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 48

 Cache Performance Example

1. Instruction Cache Miss Cycles per Instruction

Instruction Miss Cycles = I-cache miss rate× Miss penalty
=0.02×100=2

2. Data Cache Miss Cycles per Instruction

Data Miss Cycles = (Load/Store Frequency) × (D cache miss rate) × (Miss penalty)
=0.36×0.04×100=1.44

3. Actual CPI Calculation

Total CPI=Base CPI + Instruction Miss Cycles+ Data Miss Cycles
= 2 + 2 + 1.44 = 5.44

4. Speedup Calculation
Speedup = CPI with cache misses / Ideal CPI (without misses)
= 5.44/ 2=2.72 (Speedup of a perfect cache system = 2.72× faster
Average Access Time
 Hit time is also important for performance
 Average memory access time (AMAT)
 AMAT = Hit time + Miss rate × Miss penalty
 Example
 CPU with 1ns clock, hit time = 1 cycle, miss
penalty = 20 cycles, I-cache miss rate = 5%
 AMAT = 1 + 0.05 × 20 = 2ns

2 cycles per instruction

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 50

Performance Summary
 When CPU performance increased
 Miss penalty becomes more significant
 Decreasing base CPI
 Greater proportion of time spent on memory
stalls
 Increasing clock rate
 Memory stalls account for more CPU cycles
 Can’t neglect cache behavior when
evaluating system performance

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 51

Associative Caches
 Fully associative
 Allow a given block to go in any cache entry
 Requires all entries to be searched at once
 Comparator per entry (expensive)
 n-way set associative
 Each set contains n entries
 Block number determines which set

(Block number) modulo (#Sets in cache)
 Search all entries in a given set at once
 n comparators (less expensive)
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 52
Associative Cache Example

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 53

Spectrum of Associativity
 For a cache with 8 entries

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 54

 Associativity Example
 Compare 4-block caches
 Direct mapped, 2-way set associative,
fully associative
 Block access sequence: 0, 8, 0, 6, 8
 Direct mapped

Block Cache Hit/miss Cache content after access

address index 0 1 2 3

0 0 miss Mem[0]
8 0 miss Mem[8]
0 0 miss Mem[0]
6 2 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 55
 Associativity Example –Direct Mapped

Block Cache Hit/miss Cache content after access

address index 0 1 2 3

0 0 miss Mem[0]
8 0 miss Mem[8]
0 0 miss Mem[0]
6 2 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]
1.Accessing block 0 results in a miss, as the cache is initially empty. Block 0 is then loaded into cache line 0.
2.Accessing block 8 also results in a miss because block 8 maps to the same cache line as block 0 due to
direct mapping, causing block 0 to be replaced.
3.Accessing block 0 again results in another miss since it was replaced by block 8 in the previous step. Block
0 is loaded back into cache line 0, replacing block 8.
4.Accessing block 6 results in a miss since it has not been loaded into the cache yet. It is then loaded into
cache line 2, which is determined by the block address (6 mod 4 = 2).
5.Finally, accessing block 8 again results in a miss because block 0 replaced it earlier. Block 8 is loaded back
into cache line 0.
This demonstrates the limitation of direct-mapped caches, where blocks that map to the same cache line can
cause frequent cache misses if they are accessed in an alternating pattern. In this case, blocks 0 and 8 map
to cache line 0 and keep replacing each other, leading to a cache miss each time they are accessed.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 56

Associativity Example
 2-way set associative
Block Cache Hit/miss Cache content after access
address index Set 0 Set 1

0 0 miss Mem[0]
8 0 miss Mem[0] Mem[8]
0 0 hit Mem[0] Mem[8]
6 0 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]

 Fully associative
Block Hit/miss Cache content after access
address
0 miss Mem[0]
8 miss Mem[0] Mem[8]
0 hit Mem[0] Mem[8]
6 miss Mem[0] Mem[8] Mem[6]
8 hit Mem[0] Mem[8] Mem[6]

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 57

Associativity Example - 2-way associative

Block Cache Hit/miss Cache content after access

address index Set 0 Set 1

0 0 miss Mem[0]
8 0 miss Mem[0] Mem[8]
0 0 hit Mem[0] Mem[8]
6 0 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]
1.Block 0 is accessed, resulting in a miss since the cache is initially empty. Block 0 is placed in one of the
lines in set 0.
2.Block 8 is accessed and also results in a miss as it's not in the cache yet. It is placed in the other line of
set 0.
3.Block 0 is accessed again. This time, it results in a hit because it is already in set 0.

4.Block 6 is accessed, leading to a miss. Because set 0 is already full, the cache must replace one of the
blocks. According to some replacement policy (like Least Recently Used, or LRU), one of the existing
blocks (probably block 0 or block 8, depending on which was less recently used) is replaced with block 6.
In this case, block 0 is replaced.
5.Block 8 is accessed, which results in a miss since it was replaced earlier by block 6 in set 0. Block 8 is
loaded back into set 0, replacing block 6.
The advantage of 2-way set associative caches over direct-mapped caches is apparent in step 3, where a
direct-mapped cache would have resulted in a miss due to conflict, but the set associative cache gets a
hit because it can hold two blocks with the same index

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 58

Associativity Example - Fully associative

Block Hit/miss Cache content after access

address
0 miss Mem[0]
8 miss Mem[0] Mem[8]
0 hit Mem[0] Mem[8]
6 miss Mem[0] Mem[8] Mem[6]
8 hit Mem[0] Mem[8] Mem[6]
1.Block 0 is accessed and results in a miss because the cache is empty. Block 0 is placed in the first
available cache line.
2.Block 8 is accessed, resulting in a miss as it's not yet in the cache. It is placed in the next available
cache line.
3.Block 0 is accessed again. It results in a hit this time because block 0 is already in the cache.

4.Block 6 is accessed, leading to a miss since it's not in the cache. It is placed in the next available cache
line.
5.Block 8 is accessed once more. This is a hit because block 8 is still in the cache from the previous
access.
In a fully associative cache, as long as there's a free line available, new blocks are added without
replacing others. This strategy tends to have higher hit rates compared to direct-mapped or set-
associative caches, as it does not suffer from conflicts where multiple data blocks compete for the same
cache line. However, fully associative caches can be more complex and expensive to implement because
they require more hardware to search all cache lines simultaneously for a match.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 59

 How Much Associativity
 Increased associativity decreases miss rate
 But with diminishing returns (each additional increase in
associativity yields smaller reductions in the miss rate. After a certain point, the
benefits of further increasing associativity become minimal compared to the cost and
complexity it adds to the cache design)

 Simulation of a system with 64KB

D-cache, 16-word blocks, SPEC2000
 1-way: 10.3%
 2-way: 8.6%
 4-way: 8.3%
 8-way: 8.1%

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 60

Set Associative Cache Organization

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 61

 Replacement Policy
1. Direct mapped: There's only one block per set, so there's no choice in
replacement. If a block needs to be replaced, the new block simply overwrites
the existing one.
2. Set associative:
1. If there's an empty (non-valid) cache line, it's used first.

2. If all cache lines are valid, the replacement policy chooses which entry to

replace.
3. Least-recently used (LRU):
1. The cache line that hasn't been used for the longest time is replaced.

2. This is straightforward for a 2-way set associative cache and manageable

for a 4-way set associative cache but becomes complex with higher
associativity.
4. Random:
1. A random cache line within the set is chosen for replacement.

2. For caches with high associativity, random replacement can perform

similarly to LRU since tracking the least-recently used line becomes less
cost-effective.
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 62
Multilevel Caches
 Primary cache attached to CPU
 Small, but fast
 Level-2 cache services misses from
primary cache
 Larger, slower, but still faster than main
memory
 Main memory services L-2 cache misses
 Some high-end systems include L-3 cache

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 63

Multilevel Cache Example
 Given
 CPU base CPI = 1, clock rate = 4GHz
 Miss rate/instruction = 2%
 Main memory access time = 100ns
 With just primary cache
 Miss penalty = 100ns/0.25ns = 400 cycles
 Effective CPI = 1 + 0.02 × 400 = 9

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 64

Multilevel Cache Example
 Given Data:
• Base CPI = 1 (CPI without memory access delays)
• Clock Rate = 4 GHz → Clock Cycle Time = 14GHz=0.25ns
• Miss Rate per Instruction = 2% = 0.02
• Main Memory Access Time = 100 ns
 Step 1: Compute the Miss Penalty
 The Miss Penalty is the number of CPU cycles required to access main memory
when a cache miss occurs.
 Miss Penalty=Memory Access Time / Clock Cycle
=100n /s0.25ns=400 cycles
Step 2: Compute the Effective CPI
 The Effective CPI accounts for the extra cycles due to cache misses:
 Effective CPI=Base CPI+(Miss Rate×Miss Penalty)
= 1+(0.02×400) =1+8=9= 1 + 8 = 9=1+8=9

The effective CPI increases significantly due to cache misses, demonstrating the impact
of memory access delays when using only a primary cache.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 65

Example (cont.)
 Now add L-2 cache
 Access time = 5ns

 Global miss rate to main memory = 0.5%

 Primary miss with L-2 hit

 Penalty = 5ns/0.25ns = 20 cycles

 Primary miss with L-2 miss

 Extra penalty = 500 cycles

 CPI = 1 + 0.02 × 20 + 0.005 × 400 = 3.4

 Performance ratio = 9/3.4 = 2.6

This means the system with the L2 cache is 2.6 times

faster compared to the system with just L1 cache.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 66

Multilevel Cache Considerations
 Primary cache
 Focus on minimal hit time
 L-2 cache
 Focus on low miss rate to avoid main memory
access
 Hit time has less overall impact
 Results
 L-1 cache usually smaller than a single cache
 L-1 block size smaller than L-2 block size

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 67

Interactions with Advanced CPUs
 Out-of-order CPUs can execute
instructions during cache miss
 Pending store stays in load/store unit
 Dependent instructions wait in reservation
stations

Independent instructions continue
 Effect of miss depends on program data
flow
 Much harder to analyse
 Use system simulation
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 68
Interactions with Software
 Misses depend on
memory access
patterns
 Algorithm behavior
 Compiler

optimization for
memory access

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 69

Software Optimization via Blocking
 Goal: maximize accesses to data before it
is replaced
 Consider inner loops of DGEMM:

for (int j = 0; j < n; ++j)

{
double cij = C[i+j*n];
for( int k = 0; k < n; k++ )
cij += A[i+k*n] * B[k+j*n];
C[i+j*n] = cij;
}

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 70

DGEMM Access Pattern
 C, A, and B arrays

older accesses
new accesses

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 71

Cache Blocked DGEMM
1 #define BLOCKSIZE 32
2 void do_block (int n, int si, int sj, int sk, double *A, double
3 *B, double *C)
4 {
5 for (int i = si; i < si+BLOCKSIZE; ++i)
6 for (int j = sj; j < sj+BLOCKSIZE; ++j)
7 {
8 double cij = C[i+j*n];/* cij = C[i][j] */
9 for( int k = sk; k < sk+BLOCKSIZE; k++ )
10 cij += A[i+k*n] * B[k+j*n];/* cij+=A[i][k]*B[k][j] */
11 C[i+j*n] = cij;/* C[i][j] = cij */
12 }
13 }
14 void dgemm (int n, double* A, double* B, double* C)
15 {
16 for ( int sj = 0; sj < n; sj += BLOCKSIZE )
17 for ( int si = 0; si < n; si += BLOCKSIZE )
18 for ( int sk = 0; sk < n; sk += BLOCKSIZE )
19 do_block(n, si, sj, sk, A, B, C);
20 }

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 72

Blocked DGEMM Access Pattern

Unoptimized Blocked

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 73

 §5.5 Dependable Memory Hierarchy
Dependability
Service accomplishment
Service delivered
as specified
 Fault: failure of a
component
Restoration Failure  May or may not lead
to system failure

Service interruption
Deviation from
specified service

Chapter 6 — Storage and Other I/O Topics — 74

Dependability Measures
 Reliability: mean time to failure (MTTF)
 Service interruption: mean time to repair (MTTR)
 Mean time between failures
 MTBF = MTTF + MTTR
 Availability = MTTF / (MTTF + MTTR)
 Improving Availability
 Increase MTTF: fault avoidance, fault tolerance, fault
forecasting
 Reduce MTTR: improved tools and processes for
diagnosis and repair

Chapter 6 — Storage and Other I/O Topics — 75

The Hamming SEC Code
 Hamming distance
 Number of bits that are different between two
bit patterns
 Minimum distance = 2 provides single bit
error detection
 E.g. parity code
 Minimum distance = 3 provides single
error correction, 2 bit error detection

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 76

Encoding SEC
 To calculate Hamming code:
 Number bits from 1 on the left
 All bit positions that are a power 2 are parity
bits
 Each parity bit checks certain data bits:

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 77

Decoding SEC
 Value of parity bits indicates which bits are
in error
 Use numbering from encoding procedure
 E.g.

Parity bits = 0000 indicates no error

Parity bits = 1010 indicates bit 10 was flipped

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 78

SEC/DEC Code
 Add an additional parity bit for the whole word
(pn)
 Make Hamming distance = 4
 Decoding:
 Let H = SEC parity bits
 H even, pn even, no error
 H odd, pn odd, correctable single bit error
 H even, pn odd, error in pn bit
 H odd, pn even, double error occurred
 Note: ECC DRAM uses SEC/DEC with 8 bits
protecting each 64 bits
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 79
 §5.6 Virtual Machines
Virtual Machines
 Host computer emulates guest operating system
and machine resources
 Improved isolation of multiple guests
 Avoids security and reliability problems
 Aids sharing of resources
 Virtualization has some performance impact
 Feasible with modern high-performance comptuers
 Examples
 IBM VM/370 (1970s technology!)
 VMWare
 Microsoft Virtual PC
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 80
Virtual Machine Monitor
 Maps virtual resources to physical
resources
 Memory, I/O devices, CPUs
 Guest code runs on native machine in user
mode
 Traps to VMM on privileged instructions and
access to protected resources
 Guest OS may be different from host OS
 VMM handles real I/O devices
 Emulates generic virtual I/O devices for guest

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 81

Example: Timer Virtualization
 In native machine, on timer interrupt
 OS suspends current process, handles
interrupt, selects and resumes next process
 With Virtual Machine Monitor
 VMM suspends current VM, handles interrupt,
selects and resumes next VM
 If a VM requires timer interrupts
 VMM emulates a virtual timer
 Emulates interrupt for VM when physical timer
interrupt occurs
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 82
Instruction Set Support
 User and System modes
 Privileged instructions only available in
system mode
 Trap to system if executed in user mode
 All physical resources only accessible
using privileged instructions
 Including page tables, interrupt controls, I/O
registers
 Renaissance of virtualization support
 Current ISAs (e.g., x86) adapting

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 83

 §5.7 Virtual Memory
Virtual Memory
 Use main memory as a “cache” for
secondary (disk) storage

Managed jointly by CPU hardware and the
operating system (OS)
 Programs share main memory

Each gets a private virtual address space
holding its frequently used code and data

Protected from other programs
 CPU and OS translate virtual addresses to
physical addresses

VM “block” is called a page

VM translation “miss” is called a page fault
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 84
Address Translation
 Fixed-size pages (e.g., 4K)

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 85

Page Fault Penalty
 On page fault, the page must be fetched
from disk
 Takes millions of clock cycles
 Handled by OS code
 Try to minimize page fault rate
 Fully associative placement
 Smart replacement algorithms

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 86

Page Tables
 Stores placement information
 Array of page table entries, indexed by virtual
page number
 Page table register in CPU points to page
table in physical memory
 If page is present in memory
 PTE stores the physical page number
 Plus other status bits (referenced, dirty, …)
 If page is not present
 PTE can refer to location in swap space on
disk
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 87
Translation Using a Page Table

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 88

Mapping Pages to Storage

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 89

Replacement and Writes
 To reduce page fault rate, prefer least-
recently used (LRU) replacement

Reference bit (aka use bit) in PTE set to 1 on
access to page

Periodically cleared to 0 by OS

A page with reference bit = 0 has not been
used recently
 Disk writes take millions of cycles

Block at once, not individual locations

Write through is impractical

Use write-back

Dirty bit in PTE set when page is written
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 90
Fast Translation Using a TLB
 Address translation would appear to require
extra memory references
 One to access the PTE
 Then the actual memory access
 But access to page tables has good locality
 So use a fast cache of PTEs within the CPU
 Called a Translation Look-aside Buffer (TLB)
 Typical: 16–512 PTEs, 0.5–1 cycle for hit, 10–100
cycles for miss, 0.01%–1% miss rate
 Misses could be handled by hardware or software

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 91

Fast Translation Using a TLB

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 92

TLB Misses
 If page is in memory
 Load the PTE from memory and retry
 Could be handled in hardware

Can get complex for more complicated page table
structures
 Or in software

Raise a special exception, with optimized handler
 If page is not in memory (page fault)
 OS handles fetching the page and updating
the page table
 Then restart the faulting instruction
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 93
TLB Miss Handler
 TLB miss indicates
 Page present, but PTE not in TLB
 Page not preset
 Must recognize TLB miss before
destination register overwritten
 Raise exception
 Handler copies PTE from memory to TLB
 Then restarts instruction
 If page not present, page fault will occur

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 94

Page Fault Handler
 Use faulting virtual address to find PTE
 Locate page on disk
 Choose page to replace
 If dirty, write to disk first
 Read page into memory and update page
table
 Make process runnable again
 Restart from faulting instruction

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 95

TLB and Cache Interaction
 If cache tag uses
physical address
 Need to translate
before cache lookup
 Alternative: use virtual
address tag
 Complications due to
aliasing

Different virtual
addresses for shared
physical address

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 96

Memory Protection
 Different tasks can share parts of their
virtual address spaces
 But need to protect against errant access
 Requires OS assistance
 Hardware support for OS protection
 Privileged supervisor mode (aka kernel mode)
 Privileged instructions
 Page tables and other state information only
accessible in supervisor mode
 System call exception (e.g., syscall in MIPS)
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 97
 §5.8 A Common Framework for Memory Hierarchies
The Memory Hierarchy
The BIG Picture
 Common principles apply at all levels of
the memory hierarchy
 Based on notions of caching
 At each level in the hierarchy
 Block placement
 Finding a block
 Replacement on a miss
 Write policy
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 98
Block Placement
 Determined by associativity
 Direct mapped (1-way associative)

One choice for placement
 n-way set associative

n choices within a set
 Fully associative

Any location
 Higher associativity reduces miss rate
 Increases complexity, cost, and access time

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 99

Finding a Block
Associativity Location method Tag comparisons
Direct mapped Index 1
n-way set Set index, then search n
associative entries within the set
Fully associative Search all entries #entries
Full lookup table 0

 Hardware caches
 Reduce comparisons to reduce cost
 Virtual memory
 Full table lookup makes full associativity feasible
 Benefit in reduced miss rate

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 100

Replacement
 Choice of entry to replace on a miss
 Least recently used (LRU)

Complex and costly hardware for high associativity
 Random

Close to LRU, easier to implement
 Virtual memory
 LRU approximation with hardware support

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 101

Write Policy
 Write-through

Update both upper and lower levels

Simplifies replacement, but may require write
buffer
 Write-back

Update upper level only

Update lower level when block is replaced

Need to keep more state
 Virtual memory

Only write-back is feasible, given disk write
latency

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 102

Sources of Misses
 Compulsory misses (aka cold start misses)
 First access to a block
 Capacity misses
 Due to finite cache size
 A replaced block is later accessed again
 Conflict misses (aka collision misses)
 In a non-fully associative cache
 Due to competition for entries in a set
 Would not occur in a fully associative cache of
the same total size

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 103

Cache Design Trade-offs
Design change Effect on miss rate Negative performance
effect
Increase cache size Decrease capacity May increase access
misses time
Increase associativity Decrease conflict May increase access
misses time
Increase block size Decrease compulsory Increases miss
misses penalty. For very
large block size, may
increase miss rate
due to pollution.

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 104

 §5.9 Using a Finite-State Machine to Control A Simple Cache
Cache Control
 Example cache characteristics
 Direct-mapped, write-back, write allocate
 Block size: 4 words (16 bytes)
 Cache size: 16 KB (1024 blocks)
 32-bit byte addresses
 Valid bit and dirty bit per block
 Blocking cache

CPU waits until access is complete

31 10 9 4 3 0
Tag Index Offset
18 bits 10 bits 4 bits

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 105

Interface Signals

Read/Write Read/Write
Valid Valid
32 32
Address Address
32 Cache 128 Memory
CPU Write Data Write Data
32 128
Read Data Read Data
Ready Ready

Multiple cycles
per access

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 106

Finite State Machines
 Use an FSM to
sequence control steps
 Set of states, transition
on each clock edge
 State values are binary
encoded
 Current state stored in a
register
 Next state
= fn (current state,
current
inputs)
 Control output signals
= fo (current state)
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 107
Cache Controller FSM

Could partition
into separate
states to
reduce clock
cycle time

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 108

 §5.10 Parallelism and Memory Hierarchies: Cache Coherence
Cache Coherence Problem
 Suppose two CPU cores share a physical
address space
 Write-through caches

Time Event CPU A’s CPU B’s Memory

step cache cache
0 0
1 CPU A reads X 0 0
2 CPU B reads X 0 0 0

3 CPU A writes 1 to X 1 0 1

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 109

Coherence Defined
 Informally: Reads return most recently
written value
 Formally:
 P writes X; P reads X (no intervening writes)
 read returns written value

P1 writes X; P2 reads X (sufficiently later)
 read returns written value

c.f. CPU B reading X after step 3 in example

P1 writes X, P2 writes X
 all processors see writes in the same order

End up with the same final value for X

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 110

Cache Coherence Protocols
 Operations performed by caches in
multiprocessors to ensure coherence
 Migration of data to local caches

Reduces bandwidth for shared memory
 Replication of read-shared data

Reduces contention for access
 Snooping protocols
 Each cache monitors bus reads/writes
 Directory-based protocols
 Caches and memory record sharing status of
blocks in a directory
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 111
Invalidating Snooping Protocols
 Cache gets exclusive access to a block
when it is to be written
 Broadcasts an invalidate message on the bus
 Subsequent read in another cache misses

Owning cache supplies updated value
CPU activity Bus activity CPU A’s CPU B’s Memory
cache cache
0
CPU A reads X Cache miss for X 0 0
CPU B reads X Cache miss for X 0 0 0
CPU A writes 1 to X Invalidate for X 1 0
CPU B read X Cache miss for X 1 1 1

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 112

Memory Consistency
 When are writes seen by other processors
 “Seen” means a read returns the written value
 Can’t be instantaneously
 Assumptions
 A write completes only when all processors have seen
it
 A processor does not reorder writes with other
accesses
 Consequence
 P writes X then writes Y
 all processors that see new Y also see new X
 Processors can reorder reads, but not writes

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 113

 §5.13 The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
Multilevel On-Chip Caches

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 114

2-Level TLB Organization

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 115

Supporting Multiple Issue
 Both have multi-banked caches that allow
multiple accesses per cycle assuming no
bank conflicts
 Core i7 cache optimizations
 Return requested word first
 Non-blocking cache

Hit under miss

Miss under miss
 Data prefetching

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 116

 §5.14 Going Faster: Cache Blocking and Matrix Multiply
DGEMM
 Combine cache blocking and subword
parallelism

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 117

 §5.15 Fallacies and Pitfalls
Pitfalls
 Byte vs. word addressing
 Example: 32-byte direct-mapped cache,
4-byte blocks

Byte 36 maps to block 1

Word 36 maps to block 4
 Ignoring memory system effects when
writing or generating code
 Example: iterating over rows vs. columns of
arrays
 Large strides result in poor locality

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 118

Pitfalls
 In multiprocessor with shared L2 or L3
cache
 Less associativity than cores results in conflict
misses
 More cores  need to increase associativity
 Using AMAT to evaluate performance of
out-of-order processors
 Ignores effect of non-blocked accesses
 Instead, evaluate performance by simulation

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 119

Pitfalls
 Extending address range using segments
 E.g., Intel 80286
 But a segment is not always big enough
 Makes address arithmetic complicated
 Implementing a VMM on an ISA not
designed for virtualization
 E.g., non-privileged instructions accessing
hardware resources
 Either extend ISA, or require guest OS not to
use problematic instructions
Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 120
 §5.16 Concluding Remarks
Concluding Remarks
 Fast memories are small, large memories are
slow
 We really want fast, large memories 
 Caching gives this illusion 
 Principle of locality
 Programs use a small part of their memory space
frequently
 Memory hierarchy
 L1 cache  L2 cache  …  DRAM memory
 disk
 Memory system design is critical for
multiprocessors

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 121