Digital System Design

Topics to be covered
• Adders (Half, Full, Parallel Adders)
• Subtractor (Half and Full)
• N-bit Comparator
• Encoder, Decoder and Priority Encoder
• Multiplexer and DeMultiplexer
Basic Rules for Binary
Addition
1011100
1
+100111
10
A ripple carry adder is
one in which the carry
output of each full-
adder is connected to
the carry input of the
next higher order
stage. The sum and
output carry of any
stage cannot be
produced until the
carry input occurs.
Thus causing a delay in
the overall addition
process.
A look ahead carry adder can
overcome the delay of a
ripple adder. It generates a
carry either by carry
generation or by carry
propagation.
From the conditions of carry,
we can see carry is

𝐂𝐠 = 𝐀𝐁
generated when both inputs
are 1.

And carry propagates when

𝐂𝐩 = 𝐀 + 𝐁
either of the inputs or both
the inputs are 1.

𝐂𝐨𝐮𝐭 = 𝐂𝐠 + 𝐂𝐩𝐂𝐢𝐧
The carry output is
dependent on the
generated carry,
propagation carry and
carry input(CIN). The
carry generation and
carry propagation for
each stage are
immediately available as
soon as the inputs are
available.
 The Digital Comparator
Another common and very useful combinational logic circuit is that of the Digital Comparator circuit. Digital or
Binary Comparators are made up from standard AND, NOR and NOT gates that compare the digital signals
present at their input terminals and produce an output depending upon the condition of those inputs.

For example, along with being able to add and subtract binary numbers we need to be able to compare them and
determine whether the value of input A is greater than, smaller than or equal to the value at input B etc. The digital
comparator accomplishes this using several logic gates that operate on the principles of Boolean Algebra. There
are two main types of Digital Comparator available and these are.

1. Identity Comparator – an Identity Comparator is a digital comparator that has only one output terminal for
when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0
2. Magnitude Comparator – a Magnitude Comparator is a type of digital comparator that has three output
terminals, one each for equality, A = B greater than, A > B and less than A < B

The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for example A (A1,
A2, A3, …. An, etc) against that of a constant or unknown value such as B (B1, B2, B3, …. Bn, etc) and produce
an output condition or flag depending upon the result of the comparison. For example, a magnitude comparator of
two 1-bits, (A and B) inputs would produce the following three output conditions when compared to each other.

Which means: A is greater than B, A is equal to B, and A is less than B

1-bit Digital Magnitude Comparator:

Truth Table:
Logic Diagram:
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

Logic Expression:

X0 = A0B0+A0’B0’

(A=B)=X0, (A<B)= A0’B0 , (A>B)= A0B0’

2-bit Digital Magnitude Comparator:

Logic Expression: Xn= AnBn+An’Bn’ (A=B)= X1X0

(A<B)= A1’B1+X1A0’B0 (A>B)= A1B1’+X1A0B0’

Block Diagram:

Figure 2: 2 Bit Comparator

3-bit Digital Magnitude Comparator:

Logic Expression:

Xn= AnBn+An’Bn’

(A=B)=X2X1X0

(A<B)=A2’B2+X2A1’B1+X2X1A0’B0

(A>B)=A2B2’+X2A1B1’+X2X1A0B0’

Block Diagram:
5-bit Digital Magnitude Comparator:

Logic Expression:

Xn= AnBn+An’Bn’

(A=B)=X4X3X2X1 X0

(A<B)=A4’B4+X4A3’B3+X4X3A2’B2+X4X3X2A1’B1+X4X3X2X1A0’B0

(A>B)=A4B4’+X4A3B3’+X4X3A2B2’+X4X3X2A1B1’+X4X3X2X1A0B0’
DECODE
RS:
A decoder is a digital circuit that detects the presence of a specified combination of bits on its inputs

input lines to handle n-bits and 𝟐𝐧 outputs to indicate 𝟐𝐧 combinations.

and indicates the presence of that code by a specified output level. In general form, a decoder has n-

Determine the logic required to decode the Determine the logic required to decode the
binary number 1001 by producing a HIGH level on binary
the output. number 1101 and produce an active-LOW output.

Determine the logic required to decode the Determine the logic required to decode the
binary number 1011 by producing a HIGH level on binary number 1110 and produce an active-LOW
the output. output.
3-Line to 8-Line Decoding Function for Active-HIGH and Active-
LOW
Active-HIGH Active-LOW
output output
74HC154 Pin 7CHC154 Logic
Diagram Symbol
Design a 5- bit Decoder using
74HC154.

Solution:
Since the 74HC154 can handle
only 4- bits, two decoders must

expansion. The fifth bit, 𝐀𝟒, is

be used to form a 5-bit

inputs, 𝐂𝐒𝟏 and 𝐂𝐒𝟐 , of one

connected to the chip select

decoder, and 𝐀𝟒 , is connected to

the chip select inputs of the other

number is 15 or less, 𝐀𝟒 = 𝟎, the

decoder. When the decimal

lower order decoder is enabled,

and the high- order decoder is
disabled. When the decimal

𝐀𝟒 = 𝟏 and 𝐀𝟒 =0, the higher order

number is greater than 15,

is enabled, and the lower order

decoder is disabled.
Implement a Full-Adder using 3-bit decoder.

Full-Adder Logical
Full-Adder Truth Circuit
Table with Decoder
Implement the following function a
3-bit Decoder and necessary Implement the following
gates. function a 4-bit Decoder and

𝐅=𝐀+ 𝐁 𝐂
necessary gates.
𝐅 = 𝐀𝐃 + 𝐁 𝐂
𝐅=𝐀+ 𝐁 𝐂 Implement the following
∴ 𝐅 = 𝐀𝐁𝐂 + 𝐀𝐁𝐂 + 𝐀𝐁 𝐂 + 𝐀𝐁
•function
Implementa the following
3-bit Decoder and
𝐂 + 𝐀 𝐁 𝐂
function a
necessary gates.
𝐅 = 𝐁and
• 3-bit Decoder + 𝐀 𝐂
necessary
gates.
•𝐅=𝐀 +𝐂 𝐁

• Implement

BCD
ENCODERS:
An encoder is a combinational circuit that detects the presence of an active level in its input and
converts it to a coded output. E.g. Decimal to Binary encoders, Decimal to BCD encoders, Octal to
Binary encoders, Priority Encoders, Irregular Sequence Encoder etc.

4X2 Decimal to Binary

Encoder
Decimal to BCD Encoder: A decimal to BCD encoder encodes the decimal numbers to its
equivalent BCD codes.

Functions for the output

pins:
𝐀𝟑 = 𝟖 + 𝟗
𝐀𝟐 = 𝟒 + 𝟓 + 𝟔 + 𝟕
𝐀𝟏 = 𝟐 + 𝟔 + 𝟕
𝐀𝟎 = 𝟏 + 𝟑 + 𝟓 + 𝟕 + 𝟗
Octal to Binary Encoder: An Octal to Binary encoder encodes an octal number to its
equivalent binary code.

Functions for the output

pins:
𝐀𝟑 = 𝟒 + 𝟓 + 𝟔 + 𝟕
𝐀𝟏 = 𝟐 + 𝟑 + 𝟔 + 𝟕
Priority Encoder: A priority encoder also encodes a given input however, the flexibility of a
priority encoder is that, we can assign the priority of inputs. E.g Highest Priority Encoder,
Lowest Priority Encoders, Irregular Sequence Encoders.

1. Design a 4X2 Highest Priority Encoder.

2. Design a 4X2 Lowest Priority Encoder.
3. Design a Decimal to BCD Highest Priority Encoder.
4. Design a Decimal to BCD Lowest Priority Encoder.
5. Design a Decimal to BCD Irregular Sequence Encoder with priority sequence of
1,5,6,7,0,4,3,2,8,9.

Follow Class
Lecture
Multiplexer: A multiplexer is a combinational circuit which selects binary information from one of many
input lines and directs it to a single output line.
Cascading Lower Input MUX to Design Higher Input MUX

4X1 MUX with two 2X1

MUX
 Boolean Function Implementation with MUX
It is possible to design a n+1 variable Function with
2NX1 MUX.
Implement the function 𝐅 = (𝟐, 𝟑, 𝟒, 𝟔) using a MUX.
 Quadruple 2-Input Data Selector
Design
A MUX can also be considered as a data
selector. A simple 2X1 MUX can be used to
select between two 1-bit data. But what if, we
have a 2-bit data or a 4-bit data. So we can
integrate several 2X1 MUX and design
multiple-bit data selectors. The figure shows
the logical symbol of a 4-bit 2-input data
selector with an Active-Low enable input.

• Design the logical circuit for a 4-bit 2-input

data selector.

Logic Symbol of a Quadruple 2-input Data

Selector
 Demultiplexer (DEMUX): A
demultiplexer reverses the
multiplexing function. It basically
takes input from a single line and
distribute the incoming data to its
respective data line.

• Design a 3X8 Decoder Using 1X8

DEMUX.
 Textbooks:

 [1] Thomas L. Floyd, “Digital Fundamentals”

11th
edition, Prentice Hall.
 [2] M. Morris Mano, “Digital Logic &
Computer Design” Prentice Hall.