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Ece 747 Digital Signal Processing Architecture: Soc Lecture - Working With Buses & Interconnects

This document summarizes a lecture on buses and interconnects used in system-on-chip designs. It introduces the Advanced Microcontroller Bus Architecture (AMBA) specification, including the AMBA Peripheral Bus (APB), AMBA High-Performance Bus (AHB), and AMBA Extensible Interconnect (AXI). It describes the key characteristics of each bus type, such as the number of control signals, number of supported masters and slaves, transaction phases, burst lengths, and ability to perform simultaneous reads and writes. The goal is to understand the tradeoffs between these bus architectures to select the appropriate one depending on the design requirements.

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73 views25 pages

Ece 747 Digital Signal Processing Architecture: Soc Lecture - Working With Buses & Interconnects

This document summarizes a lecture on buses and interconnects used in system-on-chip designs. It introduces the Advanced Microcontroller Bus Architecture (AMBA) specification, including the AMBA Peripheral Bus (APB), AMBA High-Performance Bus (AHB), and AMBA Extensible Interconnect (AXI). It describes the key characteristics of each bus type, such as the number of control signals, number of supported masters and slaves, transaction phases, burst lengths, and ability to perform simultaneous reads and writes. The goal is to understand the tradeoffs between these bus architectures to select the appropriate one depending on the design requirements.

Uploaded by

alijanavar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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ECE 747 Digital Signal Processing Architecture

SoC Lecture Working with Buses & Interconnects


April 5, 2007 W. Rhett Davis NC State University
W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 1

Todays Lecture

Introduction
AMBA Peripheral Bus (APB) AMBA High-Performance Bus (AHB) AMBA Extensible Interconnect (AXI)

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 2

Why do we care?

What is a Bus?

What is an Interconnect?

Why do we use them?

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 3

Our Question

Which bus or interconnect should we use?

The answer depends on the following:


What IP blocks do we have and what do they work with? How many ports do we need? What kind of overhead can we permit?
Throughput Area Power
W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 4

Bus & Interconnect Standards


AMBA from ARM Wishbone from OpenCores.org CoreConnect from IBM Sonics Silicon Backplane

Well focus on AMBA in this class, because its the one our simulator models.
W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 5

AMBA Introduction

Advanced Microcontroller Bus Architecture (AMBA), created by ARM as an interface for their microprocessors. Easy to obtain documentation (free download) and can be used without royalties. Very common in commercial SoCs (e.g. Qualcomm Multimedia Cellphone SoC) AMBA 2.0 released in 1999, includes APB and AHB AMBA 3.0 released in 2003, includes AXI
NC State University ECE 747 Spring 2007 Slide 6

W. Rhett Davis

AMBA 2.0 System-Level View

Source: AMBA Specification, Rev. 2.0


W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 7

Todays Lecture

Introduction
AMBA Peripheral Bus (APB) AMBA High-Performance Bus (AHB) AMBA Extensible Interconnect (AXI)

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 8

APB Introduction
Low overhead only 4 control signals Only one master is allowed Three states: IDLE, SETUP, and ENABLE Slave is non-responsive: Transfer always takes 2 cycles

Makes timing easy to design: data is always latched between the two cycles

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 9

APB Read Transaction

Transaction takes 2 cycles: SETUP & ENABLE

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 10

APB Write Transaction

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 11

APB Performance

If AHB is high performance than APB must be low performance. What does that mean? If we were to connect an SDRAM as an APB slave from the previous lecture, what would our minimum bus clock period be?

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 12

Todays Lecture

Introduction
AMBA Peripheral Bus (APB) AMBA High-Performance Bus (AHB) AMBA Extensible Interconnect (AXI)

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 13

AHB Introduction
Larger overhead ~27 control signals Up to 15 masters allowed Split Transaction phases: Address, Data (Pipelined) HREADY signal allows insertion of waitstates

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 14

AHB Architecture
Central MUX is used, rather than a bus Achieves smaller delays than a single wire w/ tri-state buffers
Source: AMBA Specification, Rev. 2.0
W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 15

AHB Split-Transaction Bus

Address preceeds data by one cycle Mimics SDRAM operation, achieves greater data bandwidth

Source: AMBA Specification, Rev. 2.0


W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 16

Multiple Transactions w/ AHB


Source: AMBA Specification , Rev. 2.0

Addresses are pipelined to improve memory efficiency HREADY from slave allows insertion of wait states

W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 17

AHB Burst Operation

Bursts with lengths up to 32 are allowed

What would happen if an incrementing burst read to a DRAM row boundary?


NC State University ECE 747 Spring 2007 Slide 18

W. Rhett Davis

AHB Access Grant Mechanism

Bus arbitration takes extra cycles

Source: AMBA Specification, Rev. 2.0


W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 19

Todays Lecture

Introduction
AMBA Peripheral Bus (APB) AMBA High-Performance Bus (AHB) AMBA Extensible Interconnect (AXI)

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 20

AXI Introduction
Larger overhead ~77 control signals Up to 16 masters allowed 5 separate channels for address, data, and responses Not so much of an interconnect specification as a protocol (interconnect architecture is left unspecified)

W. Rhett Davis

NC State University

ECE 747

Spring 2007

Slide 21

Multi-Channel Support
Address, Data, and Response split between channels, rather than phases Allows simultaneous reads and writes

Source: AMBA AXI Protocol Specification


W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 22

AXI Read Transactions

Up to 16 transactions can be queued at once


NC State University ECE 747 Spring 2007 Slide 23

W. Rhett Davis

Multi-Layer Connectivity
Source: PL300 Technical Reference Manual

PL300 Interconnect is implemented as a crossbar: Multiple masters can talk to multiple slaves simultaneously

W. Rhett Davis NC State University ECE 747 Spring 2007 Slide 24

Comparison of AMBA Bus Types


Processors Control Signals No. of Masters No. of Slaves Interconnect Type Phases APB AHB AXI / PL300 all ARM7,9,10 ARM11 4 27 77 1 1-15 1-16 1-15 1-15 1-16 Central Central Crossbar MUX? MUX w/ 5 channels Setup, Bus request, Address, Data, Enable Address, Data Response 1 2 16 1 1-32 1-16 no no yes
ECE 747 Spring 2007 Slide 25

Xact. Depth Burst Lengths Simultaneous Read & Write


W. Rhett Davis

NC State University

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