Chapter 2

68000 Instructions Set

 The 68000 Family Instruction Set
 Assumption: Students are familiar with
the fundamentals of microprocessor
architecture
 Groups of instructions:
 Data Movement
 Arithmetic Operations
Important NOTE:
 Logical Operations The contents of the
 Shift Operations CC byte of the SR
 Bit Manipulation are updated after
 Program Control the execution of an
instruction. Refer
to Table 2.2

CpE 351 – Fall 08 2

 MOVE
 Copy information from
 MOVE.B,W,L
source to destination <Src>,<Dest>
 MOVE.L #$FFAACCDD,D0
 Comprises 70% of the
average program
 MOVE.BD0, (A0)
 All Addressing modes can be
 MOVE.W
D0,$1000(A0)
used in Source of the data.  MOVE.L D0,-$1000(A0)
 The destination could not be  MOVE.B#256,D2
 Immediate Addressing Mode  MOVE.L D0,$500(A0,D2)
 Direct Addressing Mode
 MOVE.W D0,D1
 Program Counter, Relative
Addressing Mode
 MOVE.L (A0),(A1)
 Data is examined as it is
 MOVE.B(A0,D2),(A1)
moved and condition codes  MOVE.W (A1,D0),
set accordingly (A2,D0)
X N Z V C
unaffecte update update Cleare Cleare
d d d d d

CpE 351 – Fall 08 3

 MOVEA
 MOVE TO ADDRESS REGISTER
MOVEA <ea>, An
 MOVEA $1000,A0: Set A0 to point to Address memory $1000
 MOVEA $2000,A1: Set A1 to point to Address memory $2000
 MOVEA $1000,A2: Set A0 to point to Address memory $1000
 CCR Unchanged
Address

A0 $1000

$1232

A1 $2000

$1235

A2
CpE 351 – Fall 08 4
 MOVE TO CCR
 Set to CCR a specific value
MOVE <ea>,CCR – word instruction

MOVE.W #0,CCR: Reset all flags of CCR

MOVE.W #1,CCR: Set Carry flag at 1

MOVE.W #%10,CCR: Set overflow at 1

MOVE.W #%10001,CCR: Set X and C at 1
 No move from CCR? How to read CCR?

X N Z V C

CpE 351 – Fall 08 5

 MOVE to SR
 Modify the Status byte and the CCR
MOVE <ea>,SR – in supervisor mode only;

MOVE.W #$2700,SR, $2700 = 0010 0111 0000 0000
 It is word Instruction
 Used to set the interrupt level, trace mode,
switch to user mode and adjust flags
 All addressing modes are allowed for the
source, but no addressing mode for destination
 Privilege violation trap is executed if the
processor is not in the supervisor mode

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T S I2 I1 I0 X N Z V C

CpE 351 – Fall 08 6

 MOVE from SR
 Examine the content of the status word
MOVE SR,<ea> – in user or supervisor modes;
 It is word Instruction
 All addressing modes are allowed for the
destination, but no addressing mode for
the source
 Not privileged in MC68000
 But, has become privileged in later
processors like MC68010, MC68020,
MC68030, . . .

CpE 351 – Fall 08 7

 MOVE from/to SP
 Enable the OS to manipulate user stack
 Privileged instruction, User Stack Pointer is an
operand and the second is an address register
(no other addressing mode)
 Word, longword instruction
 A7 IS Stack Pointer

USP: User Stack Pointer

SSP: Supervisor Stack pointer
MOVE.L USP, An
MOVE.L An, USP

When the 68K in the System mode, SSP is enabled

When 68K in the User Mode, USP is enabled

One of the both is enabled each time

Example:
MOVE.L USP,A3 - transfer the USP to A3

CpE 351 – Fall 08 8

 MOVEM
 MOVE MULTIPLE: Many registers are moved at the same
time to/from the memory into consecutive locations.
movem <register list>, <ea>
movem <ea>, <register list>
 Word or long word operation
 Register List: Ai-Aj/Dp-Dq
 CCR is not affected
 Effective address provides starting address
 Save and restore registers in subroutines and interrupt
services (fast context switching)
 Example:
 MOVEM.L D0-D7/A0-A6, -(SP)
 MOVEM.W (SP)+,D0-D7/A0-A6

CpE 351 – Fall 08 9

 MOVEM (contd)
 EA= -(An) Only reg-to-mem allowed, order is
A7-A0 then D7-D0
 EA= (An)+  Only mem-to-reg allowed, order is
D0-D7 then A0-A7
 EA=other  add 2 or 4 to EA, order of transfer
is D0-D7 then A0-A7

CpE 351 – Fall 08 10

 MOVEQ

Move Quick : MOVEQ #<data>, Dn
 Longword
 Moves literal (immediate value) to a data register (the
only allowed addressing modes)
 Literal is an 8-bit field within the opcode and specifies 2’s
comp. signed value (-128 to +127)
 Destination is sign-extended to 32 bits, so .L sized
 Load integer into a data register, Fast 1 word instruction,
but limited to small integers
 It affects the whole 32 bits, unlike MOVE.B
 Examples:
 MOVEQ #4, D0
 MOVEQ #%101, D2
 MOVEQ #$FA, D4
 The sign bit is expand to 32 bits
CpE 351 – Fall 08 11
 MOVEP
 Copies word or long word to/from a data register an 8-bit
peripheral
 Consecutive bytes of the peripheral are mapped into
successive odd (or even) addresses in memory
 Only one byte is moved at a time, even if you specify word
or longword operation
 Only register indirect with displacement and data register
direct are allowed for source and destination

 Example
A1= $1000
D1=$12345678
movep D1,0(A1)

$12 to loc $1000

$34 to loc $1002

$56 to loc $1004

$78 to loc $1006

CpE 351 – Fall 08 12

 LEA

Load Effective Address : LEA <ea>, An
 Longword - Can be used only with 32-bit operands
 Effective address is computed and loaded (moved) into An
 Compute once, use many
 MOVE.B D0, TABLE(PC) invalid …yes?
 Use LEA TABLE(PC), A0 then MOVE.B D0, (A0) instead

Assembly language RTL

LEA $0010FFFF,A5 [A5]$0010FFFF
Load the address $0010 FFFF into register A5.
LEA $12(A0,D4.L),A5 [A5]$12+[A0]+[D4]
Load contents of A0 plus contents of D4 plus $12 into A5.

CpE 351 – Fall 08 13

 LEA (contd)

NOTE: If the instruction MOVEA.L $12(A0,D4),A5

had been used, the contents of that address
would have been deposited in A5.

 Why use it? FASTER!

ADD.W $1C(A3,D2),D0 vs. LEA $1C(A3,D2),A5
ADD.W (A5),D0

CpE 351 – Fall 08 14

 Other Data Movement Instructions

PEA: Push Effective Address: PEA <ea>
 Calculates an effective address and pushes it onto the stack
pointed at by A7 (so, destination is implied = A7 only)
 Can be used only with 32-bit operands
 Parameter passing to subroutines, writing position independent
code

EXG Exchange : EXG Xi,Xj
 Exchanges the entire 32-bit contents of two registers
 Example: EXG D1, A3

Initially, D1=$120C5674 and A3=$3254667A

Outcome is D1=$3254667A and A3=$120C5674

SWAP: SWAP Di
 Exchanges the upper- and lower-order words of a DATA register
 Example: SWAP D1

Initially, D1=$120C5674

Outcome is D1=$5674120C
CpE 351 – Fall 08 15
 Integer Arithmetic Operations
 All Arithmetic Operations are Integer operations
 Float-point operations not directly supported
 Arithmetic Operations act on 8-, 16-, 32-bit values

Except for division, multiplication, and if destination is Ai
 ADD:
ADD <ea>, Dn
ADD Dn, <ea>
 Add source operand to destination operand and
store result in destination location
 Either source or destination must be data register

No memory-to-memory addition

CpE 351 – Fall 08 16

 ADDA
 Add source operand to content of address
register
ADDA <ea>, An
 Word, longword
 Destination is always address register
 Flags not affected, as it is not an arithmetic
operation since it is not performed on data
strings
 The entire destination register is used regardless
of the operation size is word
 Example:
ADDA.W #$123, A2

CpE 351 – Fall 08 17

 ADDQ
 adds a small 3-bit (1 to 8) literal quickly
ADDQ #<data>, <ea>
 Byte, word, longword
 3-bits integrated with the instruction word, 000
stands for 8 for fast and compact counter update
 Source is always immediate, destination any
addressing mode, except program counter relative.
 Faster than ADD, since the literal value in encoded
in the instruction
 Flags not affected if destination address register
 Word operations on address registers affects all
bits

CpE 351 – Fall 08 18

 ADDI
 Add immediate data to destination operand
 ADDI #<data>, <ea>
 Byte, word, longword
 Used to add a number to a memory content
directly
 Since not allowed using ADD

ADDI.W #$7654, $1255 ;adds value $7654 to M($1255)

CpE 351 – Fall 08 19

 ADDX
 Add source to destination along with the content
of bit X in CCR (NO ADDC, or SUBC in 68K)
ADDX Di, Dj
ADDX -(Ai), -(Aj)
 Perform multi-precision addition
 Only two modes allowed: Di and –(Ai)
 Source and destination must be the same type
 ADDX.L D3,D4 [D4] <= [D3]+[D4]+X
 Example: Add two 64-bit numbers
 First number in D1 and D0, second D3 and D2 (D1 and
D3 are the Most Significant Words)
ADD.L D0,D2
ADDX.L D1, D3
CpE 351 – Fall 08 20
 CLR
 Clear a register or memory location, it is
functionally equivalent to MOVE #0, <ea>
instruction. But it is more compact and faster.
CLR <ea>
 No argument, it is implied
 Cannot use an address register as the
destination operand i.e. can’t clear address
register.
 use SUBA.L An, An for clearing An
example: CLR.W -(A4)

CpE 351 – Fall 08 21

 DIVU / DIVS
 Carries out integer division
 DIVU: performs unsigned division
 DIVS: performs signed division
DIVU <ea>, Dn
DIVS <ea>, Dn
 Longword longword/word
 32-bit longword in Dn is divided by the 16-bit word at <ea>
 Quotient in low-order word & Remainder in high-order word of
Dn
 N and Z reflect quotient status
 During division, if quotient exceeds 16-bit, set V and terminate
 If V set, Z & N bits are undefined
 Example: assume D4=$2881E  divu #$24, D4, D4=1E1200
 Read the example in the textbook (good application)

CpE 351 – Fall 08 22

 MULU /MULS
 MULS: Multiply 2 16-bit 2’s complement
integers
 MULU: Multiply 2 unsigned integers
MULU <ea>, Dn
MULS <ea>, Dn
 Low-order 16-bit word in Dn is multiplied by the
16-bit word at <ea>
 32-bit product is deposited (saved) in Dn
 Examples:
 MULU D1, D3
 MULS #$100, D4

CpE 351 – Fall 08 23

 Subtraction
 SUB, SUBA, SUBQ, SUBI, SUBX are the
subtraction equivalent of ADD, ADDA, ADDQ,
ADDI, ADDX
 Subtracts the source operand from the
destination and places the result in the
destination
 Rules of ADD applies.
 Example: SUB.B #$30, D0  D0=D0-$30

CpE 351 – Fall 08 24

 NEG
 Forms the 2’s complement of an operand
NEG <ea>
 Subtract the destination from zero and save the
result in the destination.
 The operand’s address maybe a memory
location or a data register but not an address
register

CpE 351 – Fall 08 25

 NEGX
 Negate with Extend
 Used for multi-precision arithmetic
 Forms the 2’s complement of a byte, word, or
longword operand minus the X bit
 Finds the 2’s complement if X=0 and 1’s complement
if X=1
 If the result is nonzero, the Z bit is cleared.
Otherwise, the Z bit is cleared.

CpE 351 – Fall 08 26

 EXT
 Sign Extend a data register
EXT.W Dn
EXT.L Dn
 Sign extend a byte to word or word to longword
 EXT.W Dn copies bit 7 to bits 8-15
EXT.L Dn copies bit 15 to bits 16-31
 To signed extend 8 to 32 bit, use EXT.W
followed by EXT.L

CpE 351 – Fall 08 27

 BCD Arithmetic Operations
 Only 3 instructions support BCD (all are byte operations)
 ABCD Di,Dj or ABCD –(Ai),-(Aj)
[destination][destination]+[source]+[X]
 Add source operand to destination operand along with
extend bit.

Performs BCD arithmetic
 Used in chain arithmetic to add together strings of BCD
digits
 Why predecrement ? Big Endian, low order in higher places
 SBCD – similar to ABCD rules
[destination][destination]-[source]-[X]
 NBCD <ea>
 subtracts the specified operand from zero together with X
bit and forms the 10’s complement of the operand if X =0,
or 9’s complement if X =1
 Involve X because they are intended to be used in
operations on a stringCpE
of 351
BCD digits
– Fall 08 28
 LOGICAL OPERATIONS
 Standard AND, OR, EOR, and NOT
 AND: AND TWO NUMBERS
 OR: OR TWO NUMBERS
 EOR: XOR TWO NUMBERS
 Immediate operand versions: ANDI, ORI, EORI
 AND a bit with 0 – mask
 OR a bit with 1 – set
 EOR a bit with 1 – toggle

 Logical operations affect the CCR in the same

way as MOVE instructions

CpE 351 – Fall 08 29

 AND
AND <ea>, Dn
AND Dn, <ea>
 Byte, word, longword
 Bitwise logical AND, performing selective clear
 Not used with address register
 Destination or source must be data register
AND.B #%01001100, D1

CpE 351 – Fall 08 30

 ANDI
ANDI #<data>, <ea>
 Byte, word, longword
 Bitwise logical AND with immediate data
 Mask bits and selective clear
 Allows immediate to non data register, like
register indirect
 Example:
ANDI #$FE00, $1234
ANDI.B #$F0, (A2)+

CpE 351 – Fall 08 31

 AND Immediate to CCR/SR
ANDI #<data>, CCR
ANDI #<data>, SR
 [CCR] = [CCR] AND [literal]
 IF [S]=1 THEN [SR] = [SR] AND [literal] ELSE
TRAP
 Byte for CCR, Word for SR
 Bitwise logical AND with immediate data
 Clear selected bit in CCR or total SR
 ANDI to SR is privileged
ANDI #$FA, CCR
ANDI.W #$7FFE, SR

CpE 351 – Fall 08 32

 OR/ORI and EOR/EORI
OR <ea>, Dn EOR <ea>, Dn (non
existent)
OR Dn, <ea> EOR Dn, <ea>
ORI #<data>, <ea> EORI #<data>, <ea>
ORI #<data>, CCR EORI #<data>, CCR
ORI #<data>, SR EORI #<data>, SR
 Bitwise logical OR and EXOR
 Mask and selective set or toggle
 ORI to SR and EORI to SR are privileged , the
set works exactly like the AND set

CpE 351 – Fall 08 33

 NOT
NOT <ea>
 Byte, word, longword
 Bitwise logical NOT, it produces 1’s complement
 NEG produces 2’ complement, NOT produces
1’s complement
 NEG updates all flags of CCR, while NOT
updates only N and Z flags
NOT.B $1238
NOT.W (A7)

CpE 351 – Fall 08 34

 Logic Shift Left/Right
LSL Di, Dj
LSR Di, Dj
LSL #<data>, Di
LSR #<data>, Di
LSL <ea>
LSR <ea>
 [destination] = [destination] shifted by <count>
 Byte, word, longword for registers
 Shifts operand logically, to left or to right, by a
count
 Count: equal to [Di], #<data>[from 1 to 8] or 1,
respectively
 For memory shift, the operation size is word and
the amount of allowed shift is one
 Logical V =0 always
CpE 351 – Fall 08 35
 Logic Shift Left/Right (contd)

MOVE #35, D1 ;
LSL.W D1, D3 ;Logically shift right D3 contents 3 bits
(35-32)
MOVE.L #10, D1 ;
LSR.W D1, D6 ;Logically shift right D6 contents 10 bit
LSR.W (A1) ;Logically shift memory (A1) by 1

CpE 351 – Fall 08 36

 Arithmetic Shift Left/Right
ASL Di, Dj
ASR Di, Dj
ASL #<data>, Di
ASR #<data>, Di
ASL <ea>
ASR <ea>
 [destination] = [destination] shifted by <count>
 Byte, word, longword
 Shifts operand arithmetically, to left or to right, by a
count equal to [Di], #<data> or 1, respectively
 V=1 if the most significant two bit are different, i.e. if
MSB changes
 Memory operations restricted to word operations,
registers are sized

CpE 351 – Fall 08 37

Arithmetic Shift Left/Right (contd)

CpE 351 – Fall 08 38

 Rotate Left/Right with/without Extend
ROL Di, Dj ROXL Di, Dj
ROR Di, Dj ROXR Di, Dj
ROL #<data>, Di ROXL #<data>, Di
ROR #<data>, Di ROXR #<data>, Di
ROL <ea> ROXL <ea>
ROR <ea> ROXR <ea>
 [destination] = [destination] rotated by <count>
 Byte, word, longword
 Rotate operand to left or to right, by a count
 Only Rotate With Extend affects X
 Memory operations restricted to word operations

CpE 351 – Fall 08 39

Rotate Left/Right with/without Extend (contd)

CpE 351 – Fall 08 40

Effect of the Shift Instructions
After CCR After CCR
Initial Value First Shift XNZVC Second Shift XNZVC
ASL 11101011 11010110 11001 10101100 11001
ASL 01111110 11111100 01010 11111000 11011

ASR 11101011 11110101 11001 11111010 11001

ASR 01111110 00111111 00000 00011111 10001

LSL 11101011 11010110 11001 10101100 11001

LSL 01111110 11111100 01000 11111000 11001

LSR 11101011 01110101 10001 00111010 10001

LSR 01111110 00111111 00000 00011111 10001

ROL 11101011 11010111 ?1001 10101111 ?1001

ROL 01111110 11111100 ?1000 11111001 ?1001

ROR 11101011 11110101 ?1001 11111010 ?1001

ROR 01111110 00111111 ?0000 10011111 ?1001

CpE 351 – Fall 08 41

 Forms of Shift Operations
 Mode 1
ASL Dx,Dy Shift Dy by Dx bits

If the source is Di, then count=modulo-32 (1 to 32 bits)
 Mode 2
ASL #<data>,Dy Shift Dy by #data bits

If the source is immediate, then count=modulo-8 (1 to
8, 3 bits in the instruction)
 Mode 3
ASL <ea> Shift the contents at the
effective address by one place (If
All three
the modes apply to alliseight
source shift instructions
missing, then
count=1)
CpE 351 – Fall 08 42
 Bit Manipulation Operations
 Act on a single bit of an operand:
 The complement of the selected bit is moved to the
Z bit (Z set if specified bit is zero)

[Z] = NOT (bit number of [destination])
 The bit is either unchanged, set, cleared, or toggled
 NVCX bits are not affected
 May be applied to a bit within byte (in memory)
or a bit in a longword (in registers)

CpE 351 – Fall 08 43

 Bit Manipulation Operations (cont’d(
 All 4 have the same assembly
language forms:

BTST Dn, <ea> or BTST

#<data>,<ea>

Location of the bit to be tested

Effective address of
the operand

CpE 351 – Fall 08 44

 Bit Manipulation Operations (contd)
 BTST – Bit Test only
 BTST #4,D0

Test bit 4 on D0 if it is zero. If it is, then Z = 1, else Z = 0.
 Byte for memory, Long for registers
 Immediate data as count is assigned a second word
 Non destructive instruction program control
Loop BTST #5, (A2) ;Test bit 5 of memory (A2)
BEQ Loop ;Repeat until that bit is set

 BSET – Bit Test and Set (specified bit set)

 [Z] = NOT (bit of [destination]), bit of [destination] = 1
 BCLR – Bit Test and Clear (specified bit cleared)
 [Z] = NOT (bit of [destination]), bit of [destination] = 0
 BCHG – Bit Test and Change (specified bit toggled)
 [Z] = NOT (bit of [destination]),
 bit of [destination] = NOT (bit of [destination] )

CpE 351 – Fall 08 45

 Program Control Operations
 Examine bits in CCR and chose between two courses of
action
 CCR bits are either:
 Updated after certain instruction have been executed, or
 Explicitly updated (bit test, compare, or test instructions)
 Compare instructions: CMP, CMPA, CMPI, CMPM
 Subtract the contents of one register (or mem. location)
from another register (or mem. location)
 Update NZVC bits of the CCR
 X bit of the CCR is unaffected
 The result of subtraction is ignored

CpE 351 – Fall 08 46

 Compare
CMP <ea>, Dn
[destination] - [source]
 Byte, word, longword
 Subtract source operand from destination
operand and update flags, without writing the
result
 Program control without saving results as in
subtraction
 Destination is always Dn
 Example: CMP.W -24(A2, D3.W), D5

CpE 351 – Fall 08 47

 Compare Address
CMPA <ea>, An
[destination] - [source]
 Word, longword
 Subtract source operand from destination operand
and update flags without writing the results
 Program control without saving results as in
subtraction
 Destination is always An
 Some assemblers accept CMP with An destination
CMPA.L #$1000, A4
CMPA.W (A2)+, A6
CMPA.L D5, A2

CpE 351 – Fall 08 48

 Compare Immediate
CMPI #<data>, <ea>
[destination] - <data>
 Byte, word, longword
 Subtract source operand from destination
operand and update flags, without writing the
result
 Program control without saving results as in
subtraction
 Since it is non-destructive, PC relative is
allowed
CMPI.B #$07, D4
CMPI.W #$07, TEMP
CpE 351 – Fall 08 49
 Compare Memory-to-Memory
CMPM (Ai)+, (Aj)+
[destination] - [source]
 compares memory with memory, one of few that works
only with operands located in memory
 Byte, word, longword
 Subtract source operand from destination operand and
update flags
 Compare blocks of memory
LEA Source, A0 ;A0 points to source
LEA Destination, A1 ;A1 points to
destination
MOVE.W #Count-1, D0 ;Compare Count words
RPT CMPM.W (A0)+,(A1)+ ;Compare pair of words
DBNE D0, RPT ;Repeat until all done

CpE 351 – Fall 08 50

 Test
TST <ea>
<ea> - 0
 Byte, word, longword
 Operand compared with zero, N and Z flags of
CCR are updated
 Operand is compared with zero. No result is
saved, but contents of CCR are set according to
result.
 Effect is same as CMPI #0, <ea> except that
the CMPI instruction also sets/clears the V and
C of the CCR
TST 4(A5) ;Compare (A5) with 0 and update N an
Z
CpE 351 – Fall 08 51
 Branch Instructions
 Branch Instructions
 Branch Conditionally
 Branch Unconditionally (jump)
 Test Condition, Decrement, and Branch

CpE 351 – Fall 08 52

 Branch Conditionally
Bcc <label>
IF cc=1 (true) THEN [PC] = [PC] + d
 Byte, word

 cc stands for one of 14 logical conditions (Table 2.4)

 Based on condition cc, a branch is made forward or backward,

using 8- or 16-bit 2’s complement signed number displacement

 Assemblers compute displacement and use d8 if it fits, else d16


The displacement is the different between the current PC (i.e.
PC+2) and the <label>
 8-bit displacement can be forced by adding .S extension
 If the branch condition is set, a branch to <label> is made. If
not, the instruction immediately following the branch is
executed.
 Example
BEQ Loop ;Loop stands for disp., not its address
BCC *+8 ;If C=0 branch 8 bytes ahead of PC
 ZNCV bits are used to decide
CpE 351 – Fall 08 53
 Branch Conditions
Cond. Meaning Branch taken if:
CC Carry Clear C=0
CS Carry Set C=1
NE Not Equal Z=0
EQ Equal Z=1
PL Plus N=0
MI Minus N=1
HI Higher than C’ . Z’ = 1
LS Lower or Same C + Z = 1
GT Greater than N . V . Z’ + N’ . V’ . Z’ = 1
LT Less Than N . V’ + N’ . V = 1
GE Greater or Equal N . V’ + N’ . V = 0
LE Less or Equal Z + (N’ . V + N . V’) = 1
VC Overflow Clear V = 0
VS Overflow Set V=1
T Always True Always
F Always False Never

CpE 351 – Fall 08 54

 Singed or Unsigned?
 Information in the computer is stored in unsigned integer or
in 2’s complement forms
 Consequently, some conditional tests are intended to be
applied after operations on 2’s complement values while
others are applied after operations on unsigned integer.
Case 1 Case
2
ADD.L D0, D1 ADD.L
D0,D1
BCS ERROR BVS
ERROR
ERROR … ERROR ……
 In case 1, the numbers are interpreted as being unsigned, if
a carry is generated, the carry flag is set. Then the branch
is taken to a label to deal with out-of-range condition
 In case 2, branch is taken if overflow occurred during the
addition
 Example
 Conversion of Hex values to their ASCII equivalents
 HEX represents a single Hex character (0,1,2,…, E,F)
 And, CHAR represents its ASCII equivalent
 For example if HEX=$0A, the corresponding CHAR= $41

Solution:
MOVE.B HEX, D0 ; D0 HAS THE VALUE TO BE
CONVERTED
ADDI.B #$30, D0
CMPI.B #$39,D0 ; TEST VALUES IN THE RANGE OF $A
TO $F
BLT EXIT ; EXIT IF NOT IN THE RANGE
ADDQ #$7,D0 ; ELSE ADD 7
EXIT MOVE.B DO, CHAR
 In the example above, when the BLT will be taken?
i.e when D0 <$39 or when D0>$39
 Branch Unconditionally
 BRA <label> or JMP (An)
JMP d16(An)
JMP d8(An,Xi)
JMP Absolute_address
JMP d16(PC)
JMP d8(PC,Xi)
 JMP <ea> [PC] = <ea>
 Unsized
 Program execution continues at the effective
address specified by the instruction, Its like a
GOTO
 BRA = JMP, but BRA always relative with d8 or d16
 Arguments of JMP is a displacement or absolute
 Typical application of BRA is the SWITCH and
BREAK statements

CpE 351 – Fall 08 57

 Example
 * HLL CASE construct mapped to assembly
 *
CASE MOVE.B TEST, D0 ;Put value to test
BEQ ACTION0 ;Take if argument=0
SUBQ.B #1, D0
BEQ ACTION1 ;Take if argument=1
SUBQ.B #1, D0
BEQ ACTION2 ;Take if argument=2
EXCEPTION . . . ;No known match, an exception
...
BRA EXIT ;Leave case
ACTION0 ... ;Perform the proper action, then
BRA EXIT ;Leave thorough the door
ACTION1 . . .
BRA EXIT
ACTION2 . . .
BRA EXIT
... ;Other ACTIONS
EXIT ... ;Single exit point for case

CpE 351 – Fall 08 58

 DBcc
 Test Condition, Decrement, and branch
 Powerful instruction to implement loops
DBcc Dn,<label> (16 bit displacement only)

One of 14 values from Table 2.4, plus T, plus F

If test is TRUE, branch is NOT taken !

If cc is NOT TRUE, Dn is decremented by 1;
If Dn is now equal to –1 next instruction is executed
if not, branch to <label is taken>
 First, carry out the test defined by CC
 If true, the branch is not taken, and the next instruction
in sequence is executed
 If false, the low order 16 bits of Dn is decremented. If the
resulting content is equal to -1, the next instruction in
sequence is executed
 Otherwise, the branch to <label> is made
 DBcc (contd)
 Put it this way
 IF condition false, then decrement register, if not negative
then take the branch
 Automatic looping facility; replaces set of
instructions
 Decrement counter
 Test a condition
 Branch
 Only one word counter allowed as Dn, for fast
decrement since MC68000 is 16-bit inside
 Label is 16-bit signed value, and cc can be T or F
 It works on the opposite sense of BRA, BCC branches
of carry clear, while DBCC exits if carry clear
 DBcc Example
* DBcc example
*
MOVE.W #255, D1
WAIT BTST.B #0, READY
BEQ WAIT
MOVE.W INPUT, D0
.
.
CMPI.W #$FFFF, D0
DBEQ D1, WAIT
When ready, input data is read and tested to see if it
is equal $FFFF, if so we terminate else repeat on
new data items for up to 256 times
 Set Byte Conditionally
Scc <ea>
IF cc=1 THEN [destination] = 11111111
ELSE [destination] = 00000000
 Byte
 Condition is tested, and specified destinations
receives $FF or $00 based on being True or False
 Synchronization and general control via flags
 Compact and fast compared to equivalent
sequence
 All 16 conditions can be used (including T and F)
SPL.B Flag
SCC.B 3 (A1,D3.W)
CpE 351 – Fall 08 62
 Test And Set
TAS <ea>
 [CCR] = tested ([operand]) and [destination(7)] = 1
 Byte
 Test byte specified by <ea> and update Z and N flags of
CCR accordingly,
 Bit 7 (MSB) of the operand is set to 1
 Synchronization in shared memory access and OS
complex commands
 Affects N and Z, V and C are cleared, X unaffected
 Indivisible or atomic, it uses read-modify-write cycle
without interruption
TAS.B Semaphore
TAS.B 3(A1,D3.W)
 Return from Exception/Subroutine
RTE Return from Exception
RTS Return from Subroutine
RTR Return and Restore CCR
 RTE
 IF [S] = 1 THEN
 [SR] = M[([SP])]; [SP] = [SP]+2;
 [PC] = M[([SP])]; [SP] = [SP]+4;
 ELSE TRAP
 Adjust SSP/USP to restore SR and PC for RTE, PC for RTS,
CCR
 and PC for RTR. Only RTE is privileged
 Terminate subroutines and exceptions
 SR saved automatically upon entering exception
 CCR is the users’ baby, if you want to restore
 Reset & NO Operation
RESET
 IF [S] = 1 THEN Reset* output pin = low for 124 clocks,
ELSE TRAP
 Privileged Instruction
 Assert Reset* line, causing devices connected to reset
 Does not affect CPU itself
 Used RESET for Peripheral to be reconfigured after crash

NOP
 No effect on the CPU other than advancing the PC to the
next instruction
 Waste time and memory space
 Sometimes used to generate delays.
 Sometimes it is replaced with future code.
 Stop
STOP #<data>
 IF [S] = 1 THEN [SR] = <data> ELSE TRAP
 Loads <data> into SR, advance PC then freeze
 Resumes execution when an interrupt or a reset
exception occurs
 Privileged instruction
 A trace exception begins when STOP starts
executing if the T bit is enabled
 Interrupts higher than current level get
serviced, others ignored
 Used for Debugging
 Trap and Trap on Overflow
TRAP #<vector>
 [SSP] = [SSP] - 4; [M([SSP])] = [PC];
 [SSP] = [SSP] - 2; [M([SSP])] = [SR];
 [S] = 1;
 [PC] = address (vector);
 Generate an exception, first it switches to supervisor
mode, save PC on stack, then gets the address of the
exception show specified by vector (0, 1 , 2, … , 15)
 Debugging, Print/Display Services like your simulator
 Interrupts higher than current level get serviced, others
ignored
 S bit is restored upon executing RTE at the end of
exception
 SSP is used, even if S is not 1 upon starting TRAP
 TRAPV is a dedicated one, no vector, and gets executed
only if V=1
 Check Register Against Bounds
 CHK <ea>, Dn
 Check the low order word of Dn against two
bounds
 If Dn(0:15) < 0 OR Dn(0:15) > <ea> then a call to OS
is made
 Else, next instruction in sequence is executed
 Used by compilers to test whether an array is
being accessed outside its declared bounds
 Subroutines
 Subroutine is a coherent sequence of instructions that can
be called from some point in a program to carry out a well
defined function, preferably single one
 This allows using the sequence many times without writing
it as many
 It makes the program modular, hence more readable and
maintainable
 Usually have entry point and exit point
 One may or may not need input data, and may or may not
return data
 Subroutines can be nested, one calling another
 Subroutine can be recursive, one calling itself many times
 Subroutine with destructive register access, must save
registers and CCR upon entering and restore upon exiting,
along with CCR
 Subroutines
 BRANCH TO SUBROUTINE
BSR <label> = [A7] [A7] - 4
M([A7])] [PC]
[PC] [PC] + d8

 RETURN FROM SUBROUTINE

RTS = [PC] [M([A7])]
[A7] [A7] + 4

CpE 351 – Fall 08 70

 Subroutines, cont’d
 BRANCH TO SUBROUTINE
 Simply, load the PC with the starting address of the subroutine
000FFA 41F900004000 LEA TABLE, A0
001000 61000206 NextChr BSR GetChar
001004 10C0 MOVE.B D0,(A0)
001006 0C00000D CMP.B #$0D,D0
00100A 66F4 BNE NextChr
.
.
001102 61000104 BSR GetChr
001106 0C000051 CMP.B #’Q’,D0
00110A 67000EF4 BEQ QUIT
.
.
001208 1239000080000 GetChr MOVE.B ACIAC,D0

BSR d8 d8=? (or d16, to specify d8 use BSR.S)

d8 = $00001208 – ($00001000 + 2) = $00000206

current PC value

CpE 351 – Fall 08 71

Nested Subroutines

CpE 351 – Fall 08 72

Nested Subroutines, cont’d

CpE 351 – Fall 08 73

 Nested Subroutines, cont’d
 Returning directly to a higher-level subroutine
Sub2 .
.
BEQ Exit
.
.
RTS
Exit LEA 4(A7),A7
RTS

 RTR (Return and restore condition codes)

 Save the condition code register on the stack:
MOVE CCR, -(A7)
 Use RTR instead of RTS

CpE 351 – Fall 08 74