I2C PROTOCOL

PROTOCOL???

TYPES:
I. INTER SYSTEM
PROTOCOL
II. INTRA SYSTEM
THUMB RULE FOR ANY LEARNING
 1-WIRE INTERFACE (OPTIONAL)
• 1-WIRE PROTOCOL BY DALLAS SEMICONDUCTOR
• NO CLOCK AND ONLY ONE DATA LINE
• HALF DUPLEX, BIDIRECTIONAL, LOW SPEED AND POWER
• LONG DISTANCE SERIAL DATA COMMUNICATION
• ONLY MASTER- SLAVE CONFIGURATION – ONE MASTER AND UPTO 100 SLAVE DEVICE
• DOESNOT USE CLOCK SIGNAL INSTEAD SLAVE DEVICES ARE INTERNALLY CLOCKED
AND SYNCHRONIZED WITH A SIGNAL FROM THE MASTER DEVICE
• TYPICAL DATA SPEED – 15.4KBPS AND MAXIMUM 125KBPS
 I2C – INTER-INTEGRATED CIRCUITS – IIC OR
TWI
• WHO – PHILIPS SEMICONDUCTOR (NOW NXP SEMICONDUCTORS), ATMEGA,
INTEL
• WHEN – 1982, 1992, 1995
• WHY – ESTABLISH COMMUNICATION BETWEEN TWO OR MORE IC
• WHERE – EEPROM, I/O INTERFACES, PERIPHERAL DEVICES
CONTROLLER AS MASTER & PERIPHERAL DEVICES AS SLAVES
 WHAT
• SYNCHRONOUS – SENDER GETS ACK RESPONSE FROM RECEIVER WHEN DATA RECEIVED
SUCCESSFULLY
• HALF DUPLEX BIDIRECTIONAL – DATA FLOW FROM MASTER TO SLAVE OR SLAVE TO
MASTER
• MULTI-CONTROLLER/MULTI-TARGET (MASTER/SLAVE)
• PACKET SWITCHED
• SINGLE-ENDED
• SERIAL COMMUNICATION BUS (TWO WIRED –SDA, SCL)
• BUILT IN COLLISION DETECTION
• CLOCK FREQUENCY – (0-1MHZ) DRIVING AT 30 MILLI AMPS
• OPERATING TEMP - -40 TO +85 DEGREE CELSIUS
• MODES – STANDARD AND FAST COMMONLY USED
• DEVICES – 128 DEVICE (7 BIT ADDRESSING – 0-127 (2^7))
OVERCOME LIMITATION BASED ON OTHER MODES 8,10 BIT ADDRESSING
(8 BIT – 2^8, 10 BIT – 2^10)
 I2C Mode Speed
Standard Mode 100 kbps
Fast Mode 400 kbps
Fast Mode Plus 1 Mbps
High Speed Mode 3.4 Mbps
Ultra-Fast Mode 5 Mbps

• I2C BUS LENGTH – 1 MTR AT 100KBAUD, 10 MTR AT 10KBAUD

• ARDUINO CAN SUPPORT ONLY 100K AND 400KBITS

APPLICATIONS OF I2C INTERFACE

• ATMEL AT24CXX EEPROM CHIPS
• MAXIM DS1307/8 REAL TIME CLOCK CHIPS
• MICROCHIP MCP7941X REAL TIME CLOCK CHIPS
• MCP23017 PORT EXPANDER
• PCA85276 40×2 LCD DRIVE
 HOW I2C WORKS
• I2C DATA TRANSFERRED IN MESSAGES.
• MESSAGES BROKEN UPTO INTO FRAMES OF DATA
• EACH MESSAGE HAS ADDRESS FRAME THAT CONTAINS BINARY ADDRESS OF SLAVE
• MESSAGE ALSO INCLUDE START AND STOP CONDITION,READ/WRITE BITS, ACK/NACK BITS
EACH DATA FRAME
• START CONDITION: THE SDA LINE SWITCHES FROM A HIGH VOLTAGE LEVEL TO A
LOW VOLTAGE LEVEL BEFORE THE SCL LINE SWITCHES FROM HIGH TO LOW.
• STOP CONDITION: THE SDA LINE SWITCHES FROM A LOW VOLTAGE LEVEL TO A
HIGH VOLTAGE LEVEL AFTER THE SCL LINE SWITCHES FROM LOW TO HIGH.
• ADDRESS FRAME: A 7 OR 10 BIT SEQUENCE UNIQUE TO EACH SLAVE THAT
IDENTIFIES THE SLAVE WHEN THE MASTER WANTS TO TALK TO IT.
• READ/WRITE BIT: A SINGLE BIT SPECIFYING WHETHER THE MASTER IS SENDING
DATA TO THE SLAVE (LOW VOLTAGE LEVEL) OR REQUESTING DATA FROM IT (HIGH
VOLTAGE LEVEL).
• ACK/NACK BIT: EACH FRAME IN A MESSAGE IS FOLLOWED BY AN ACKNOWLEDGE/NO-
ACKNOWLEDGE BIT. IF AN ADDRESS FRAME OR DATA FRAME WAS SUCCESSFULLY
RECEIVED, AN ACK BIT IS RETURNED TO THE SENDER FROM THE RECEIVING DEVICE.
 FEATURES OF I2C
• HALF DUPLEX COMMUNICATION- BIDIRECTIONAL IS POSSIBLE BUT NOT SIMULTANEOUSLY
• SYNCHRONOUS COMMUNICATION – DATA TRANSFERRED IN FORM OF FRAMES OR BLOCKS
• CONFIGURATION- MULTI-MASTER, MULTI-SLAVE
• CLOCK STRETCHING – SLAVE DEVICE NOT ACCEPT MORE DATA TO HOLD WHEN SCL LINE
LOW, TO DISABLE MASTER RAISE THE CLOCK LINE
MASTER – NOT ABLE TO RAISE CLOCK LINE BECAUSE WIRES ARE AND WIRED AND WAIT
UNTIL SLAVE RELEASES SCL LINE TO SHOW ITS READY TO TRANSFER NEXT BIT
• ARBITRATION:- I2C SUPPORTS MULTI-MASTER BUS SYSTEM BUT MORE THAN ONE BUS CAN
NOT BE USED SIMULTANEOUSLY. SDA & SCL ARE MONITORED BY MASTERS.
IF SDA IS FOUND HIGH WHEN IT SUPPOSED TO BE LOW, IT INFERRED AS ANOTHER MASTER
IS ACTIVE AND IT STOPS THE TRANSFER OF DATA
• USES SERIAL TRANSMISSION FOR TRANSMISSION OF DATA
• USED FOR LOW SPEED COMMUNICATION
 VALUE OF RESISTOR

1K8,4K7 AND 10K ARE COMMON VALUES

1K8 RESISTOR GIVES BEST PERFORMANCE (low RESISTANCE faster COMMUNICATION)

IF RESISTORS MISSING, SCL & SDA LINES ALWAYS LOW – NEARLY 0 VOLTS AND I2C BUS WILL
NOT WORK
 STEPS OF I2C DATA TRANSMISSION
1. The master sends the start condition to every connected slave by switching the SDA line
from a high voltage level to a low voltage level before switching the SCL line from high to
low

2. The master sends each slave the 7 or 10 bit address of the slave it wants to
communicate with, along with the read/write bit
3. Each slave compares the address sent from the master to its own address. If the
address matches, the slave returns an ACK bit by pulling the SDA line low for one bit. If the
address from the master does not match the slave’s own address, the slave leaves the
SDA line high

4. The master sends or receives the data frame:

5. After each data frame has been transferred, the receiving device returns another ACK bit
to the sender to acknowledge successful receipt of the frame

6. To stop the data transmission, the master sends a stop condition to the slave by
switching SCL high before switching SDA high
 SINGLE MASTER WITH
MULTIPLE
Because I2C uses addressing, multiple SLAVES
slaves can be controlled from a single master. With a 7 bit
address, 128 (27) unique address are available. Using 10 bit addresses is uncommon, but provides
1,024 (210) unique addresses.
To connect multiple slaves to a single master, wire them like this, with 4.7K Ohm pull-up resistors
connecting the SDA and SCL lines to Vcc:
 MULTIPLE MASTERS WITH MULTIPLE SLAVES
Multiple masters can be connected to a single slave or multiple slaves.
Problem: When two masters try to send or receive data at the same time over the SDA line.
Solution: Each master needs to detect if the SDA line is low or high before transmitting a message.
If the SDA line is low, this means that another master has control of the bus, and the master should
wait to send the message.
If the SDA line is high, then it’s safe to transmit the message.
To connect multiple masters to multiple slaves, use the following diagram, with 4.7K Ohm pull-up
resistors connecting the SDA and SCL lines to Vcc:
EXAMPLE
 I2C HARDWARE DESIGN - PHYSICAL
LAYER
VDD I2C System Features
SDA

Only two communication

SCL
lines for all devices on
the bus (SDA, SCL)
VDD

VDD
VDD

VDD
SDA

SDA

SDA

SDA
SCL

SCL
SCL

SCL
Bi-directional
communication, half
Microcontroller Microcontroller ADC DAC
Controller 1 Controller 2 Target 1 Target 2

duplex
Allows for multiple
GND

GND

GND

GND
controllers and multiple
GND targets
GND

Requires pull-up
resistors on both SDA
and SCL
1
9
I2C PHYSICAL LAYER – OPEN-DRAIN
CONNECTION
VD When NMOS turns
D Pull- ON, SDA or SCL is
up
SDA, resisto
pulled low
r
SCL SDA, SCL
Voltage VDD
Device
I2C
logic
GN
D
Open- GND Quick transition from high to low as NMOS
drain
connectio
pulls charge from any bus capacitance
n from SDA, SCL

2
0
I2C PHYSICAL LAYER – OPEN-DRAIN
CONNECTION
VD When NMOS turns OFF,
D Pull- SDA or SCL is released and
up
SDA, resisto
returns high from the pullup
r resistor
SCL

SDA, SCL Voltage

VD
Device
D
I2C
logic
GN
D
Open- GND Exponential rise depends on capacitance
drain
connectio
on SDA or SCL and pullup resistor size
n
Low resistance: faster communication, more
power High resistance: slower
communication, less power 9
 I2C PHYSICAL LAYER – OPEN COLLECTOR VS
PUSH-PULL Open Drain
VDD VDD

• Open drain output

Open Drain can connect
Device
SDA
Device
together
I2C
logic On
Any output that
goes low takes Off
I2C
logic
• Any output that goes
priority
Q1 Q2
low will pull the bus
Open-
drain
GND GND Open-
drain
low
connectio
n VD VD
connectio
n • This type of
Push-Pull
Push Pull

D D
Q1 Q3 connection is called a
• Open drain output
Device
On Off
“wired-OR”
cannot connect
Device
I2C I2C
logic Off On logic
Bus Contention
Q2 Output at
indeterminate
Q4 together
Push-Pull GND
state
GND Push-Pull
• Connecting outputs
Output
Output
tries to
dive high tries to
dive low
together can cause a
bus contention where
the output state is
indeterminate
 DESIGN (ARCHITECTURE)
• BUS HAS TWO ROLES FOR NODES: MASTER AND SLAVE
• MASTER NODE – NODE GENERATES THE CLOCK AND INITIATES COMMUNICATION
WITH SLAVE
• SLAVE NODE – NODE THAT RECEIVES THE CLOCK AND RESPOND WHEN
ADDRESSED BY MASTER

• 4 POTENTIAL MODES OF OPERATION FOR BUS DEVICE, MOST DEVICE USE A SINGLE
ROLE AND TWO MODES
• MASTER TRANSMIT – MASTER NODE SENDING DATA TO SLAVE
• MASTER RECEIVE - MASTER NODE RECEIVING DATA TO SLAVE
• SLAVE TRANSMIT - SLAVE NODE SENDING DATA TO MASTER
• SLAVE RECEIVE - SLAVE NODE RECEIVING DATA TO MASTER
BUILDING BLOCKS OF I2C SERIAL
INTERFACE
 ADVANTAGE OF I2C
• I2C REQUIRES TWO SIGNALS/PINS TO COMMUNICATE NUMEROUS DEVICES
• USES CHIP ADDRESSING, WE ADD ADDITIONAL DEVICES TO BUS– NO NEED OF
WIRING
• DEVICE CAN WORK AS BOTH MASTER AND SLAVE
• EMPLOYS BETTER ERROR HANDLING FUNCTIONALITY
DISADVANTAGE OF I2C

• DUE TO PULL UP RESISTOR – CLOCK SPEED LIMITATION AND POWER DISSIPATION

• COMPLEX HARDWARE AND FIRMWARE COMPARED TO UART, SPI
• HALF DUPLEX PROTOCOL WHICH ADDS COMPLEXITY
• SLOWER DATA TRANSFER RATE THAN SPI
• SIZE OF DATA FRAME IS LIMITED TO 8BITS
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
1. Before the address frame of I2C communication, what actions
make up the START condition?
a. The controller device sets the SDA low, and then sets the SCL low
b. The controller device sets the SCL low, and then sets the SDA low
c. The controller device sets the SCL low, and the target device pulls the
SDA low as an ACK
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
1. Before the address frame of I2C communication, what actions
make up the START condition?
a. The controller device sets the SDA low, and then sets the SCL low
b. The controller device sets the SCL low, and then sets the SDA low
c. The controller device sets the SCL low, and the target device pulls the
SDA low as an ACK

SDA

SCL
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
2. In the address frame, after the controller device sends the 7 bit
address, what is the next part of the I2C protocol sent?
a. The target device sends the ACK to acknowledge the communication
coming from the controller device
b. The controller device sends the R/W bit to indicate if it wants to read from
or write to the target device
c. The controller device send a STOP condition before sending the next data
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
2. In the address frame, after the controller device sends the 7 bit
address, what is the next part of the I2C protocol sent?
a. The target device sends the ACK to acknowledge the communication
coming from the controller device
b. The controller device sends the R/W bit to indicate if it wants to read from
or write to the target device
c. The controller device send a STOP condition before sending the next data

A6 A5 A4 A3 A2 A1 A0
R/W
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
3. Because of the NMOS open-drain connection to SDA and SCL,
which part of the communication waveform is faster?
a. The rise time of SDA and SCL
b. The fall time of SDA and SCL
c. The rise time and fall time of SDA and SCL are the same
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
3. Because of the NMOS open-drain connection to SDA and SCL,
which part of the communication waveform is faster?
a. The rise time of SDA and SCL
b. The fall time of SDA and SCL
c. The rise time and fall time of SDA and SCL are the same

SDA, SCL
Voltage VDD

GND

Open-drain connections are actively pulled

down
instead and are faster than a resistive pull
up
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
4. What is the benefit of having an open-drain connection over push-
pull outputs for I2C?
a. High speed drive for the bus outputs
b. Reduction of bus capacitance
c. Prevents destructive current draw during bus contention when
outputs are tied together
 QUIZ: BASICS OF I2C: THE I2C
PROTOCOL
4. What is the benefit of having an open-drain connection over push-
pull outputs for I2C?
a. High speed drive for the bus outputs
b. Reduction of bus capacitance
c. Prevents destructive current draw during bus contention when
outputs are tied together

Push-Pull outputs may pull a large current

when the outputs are tied together and
there is bus contention
 SUMMARY
•MASTER DEVICE WRITES DATA TO THE SLAVE DEVICE:

•THE MASTER DEVICE READS DATA FROM THE SLAVE DEVICE:

•MESSAGE FORMAT OF I2C BUS

TIMING DIAGRAM
CLOCK STRETCHING
In the above figure, 3 Masters are try to send the slave address through the bus
simultaneously. So All 3 masters send the first MSB. Although all having their MSB 1, so
no one can lose its arbitration. When any master sends the 0 bit first then it wins the
ARDUINO AVR REGISTER CONFIGURATION
ARDUINO I2C PINS
 WIRE LIBRARY
• BUILT-IN ARDUINO LIBRARY FOR I2C INTERFACE
• HEADER – WIRE.H HAS ALL FUNCTIONS RELATED TO I2C
• JOIN DEVICE ON I2C BUS

WIRE.BEGIN(ADDRESS) – OPTIONAL FOR MASTER NEEDED FOR SLAVE AND WIRE.BEGIN() -

MASTER
• SENDING DATA OVER I2C – 3 FUNCTIONS
Wire.beginTransmission() – 1. It informs the bus that we will be sending the data
2. It notifies the slave to prepare to receive the data
Wire.write() – wire.write(value) – that stores the data we want to send
Wire.endTransmission() – after sending data free up network for allowing other devices to communicate

• RECEIVE DATA OVER I2C – 3 FUNCTIONS

Wire.requestFrom() – request data from slave device wire.requestform(address,quantity)
Eg: wire.requestform(0x08,1) – request one byte of data from slave 0x08
Wire.available() – to check data available on the bus – returns no of bytes waiting to read
Wire.read() – gets only one byte of data from the I2C bus

• EVENT HANDLERS – MANAGE DATA RECEIVED FROM OTHER DEVICES IN I2C NETWORK

WIRE.ONRECEIVE(HANDLER) – TO REGISTER A FUNCTION THAT WILL MANAGE DATA RECEIVED

WIRE.ONREQUEST() – USED ON SLAVE DEVICE - ONREQUEST(FUNCTION) ONLY CONTAINS WIRE.WRITE

 I2C SCANNER
• TO CHECK THE ADDRESS OF VARIOUS I2C MODULES – I2C SCANNER WITH SOFTWIRE
LIBRARY
• SCANNER – WILL CYCLE THROUGH ALL POSSIBLE I2C ADDRESSES AND ONCE IT
RECEIVES A RESPONSE FROM THE DEVICE – IT INFORM WORKING ADDRESS
• WHAT IF TWO DEVICES HAVE SAME ADDRESSES?? SELECT AN ALTERNATE ADDRESS FOR
ONE DEVICE
EG: I2C LCD ADAPTER – 0X27 ADDRESS. ALTERNATE ADDRESS BASED ON A0,A1,A2 –
CREATE SHORTS BETWEEN THESE PADS OR USE JUMPER OR SWITCHES

• SNIFFER – PASSIVELY LISTEN TO SIGNALS ON THE BUS AND DETECTS THE RESPONSIBLE
DEVICE EVEN IF CHIP NOT KNOWN
 I2C REGISTER

• TWI BIT RATE REGISTER

• TWI CONTROL REGISTER
• TWI STATUS REGISTER
• TWI DATA REGISTER
• TWI (SLAVE) ADDRESS REGISTER
• TWI (SLAVE) ADDRESS MASK REGISTER