UNIT 4:

ROUTING
 ROUTING
• In the placement phase, the exact locations of circuit blocks and pins are determined.
• A netlist is also generated which specifies the required interconnections.
• Space not occupied by the blocks can be viewed as a collection of regions. These regions are
used for routing and are called as routing regions.
• The process of finding the geometric layouts of all the nets is called routing.
• Nets must be routed within the routing regions. In addition, nets must not short-circuit, that
is, nets must not intersect each other.
• The input to the general routing problem is:
1. Netlist
2. Timing budget for nets, typically for critical nets only,
3. Placement information including location of blocks, locations of pins on the block
boundary as well as on top, location of I/O pins on the chip boundary as well as on top
4. RC delay per unit length on each metal layer, as well as RC delay for each type of via.
 ROUTING
• The objective of the routing problem is dependent on the nature of the chip.
• For general purpose chips, it is sufficient to minimize the total wire length, while completing
all the connections.
• For high performance chips, it is important to route each net such that it meets its timing
budget.
• Usually routing involves special treatment of such nets as clock nets, power and ground
nets. In fact, these nets are routed separately by special routers.
• A VLSI chip may contain several million transistors. As a result, tens of thousands of nets
have to be routed to complete the layout.
• In addition, there may be several hundreds of possible routes for each net. This makes the
routing problem computationally hard.
• One approach to the general routing problem is called Area Routing, which is a single-phase
routing technique. This technique routes one net at a time considering all the routing
regions. However, this technique is computationally infeasible for an entire VLSI chip and is
typically used for specialized problems, and smaller routing regions.
 ROUTING
• The traditional approach to routing, however, divides the routing into two phases.
• The first phase is called global routing and generates a ‘loose’ route for each net. In fact, it
assigns a list of routing regions to each net without specifying the actual geometric layout
of wires.
• The second phase, which is called detailed (local) routing, finds the actual geometric layout
of each net within the assigned routing regions.
• Unlike global routing, which considers the entire layout, a detailed router considers just one
region at a time. The exact layout is produced for each wire segment assigned to a region,
and vias are inserted to complete the layout.
 GLOBAL ROUTING
Global routing is divided into three distinct phases:
a) Region Definition:
• The entire routing space is partitioned into routing regions to organize the connections
efficiently.
• Routing occurs between blocks and above blocks (Over-the-Cell or OTC areas).
b) Region Assignment:
• Determines which nets (electrical connections) will be routed through which regions.
• Ensures optimal wire usage to minimize congestion and delays.
c) Pin Assignment:
• Assigns pins (connection points) to specific locations in each routing region.
• Ensures that connections between different routing regions are properly established.
 GLOBAL ROUTING
The routing space consists of different routing regions, which determine how interconnections are
established:
a) Channels
• Definition: Rectangular areas between two blocks where routing occurs.
• Capacity: Defined by the number of layers (l) available for routing and depends on the height of
the channel and wire width/spacing.
• Example: If a channel has 2 metal layers (M1, M2) available, its capacity is determined by the
number of wires that can be routed within those layers.
• Some channels have pins in the middle, which connect to 3D-switchboxes for further routing.
b) 2D-Switchboxes:
• Definition: A rectangular routing region completely enclosed by blocks on all four sides.
• Features: Has pins on all four sides for routing connections. Also contains pins in the middle,
which allow connections to 3D-switchboxes.
c) 3D-Switchboxes: A three-dimensional routing region with pins on all six sides.
 Local Routing Problems
Local routing problems in VLSI design arise due to various constraints and parameters. These
parameters define different routing challenges, each requiring specific solutions. Below is a
structured breakdown of the key parameters influencing local routing problems:
a) Number of Wiring Layers:
• The number of layers available depends on the fabrication technology and design style. Earlier
technologies had only two layers, but modern technologies support multiple layers.
• Vias: A via is a contact cut that connects two different layers.
b) Wire Orientation in Layers:
• In reserved-layer routing, each layer is restricted to a specific direction: One layer has only
horizontal wires. Another layer has only vertical wires.
• Some technologies allow wire segments to be placed at multiples of 45° for more flexibility.
c) Gridded vs. Gridless Routing:
Gridded Routing: Wire segments follow a fixed orthogonal grid with uniform spacing.
Gridless Routing: Wires of different widths and contacts (vias) are explicitly represented.
 Local Routing Problems
d) Presence of Obstacles:
• Routing can be done in a fully available area or an area with blockages due to pre-existing
circuits or design constraints.
e) Terminal Positioning
• Fixed terminals: The terminal locations are predefined and cannot be moved.
• Floating terminals: The router can move terminals within a restricted area to optimize routing.
f) Terminal Permutability:
• Sometimes, terminals can be interchanged if they are functionally equivalent.
• Example: The two inputs of an NAND gate can be swapped.