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Module 5 - Pentium

The document provides an overview of Intel's Pentium processors, detailing their evolution from the original Pentium in 1993 to the Pentium 4, highlighting their architecture, features like MMX technology, and the advantages of superscalar processing. It also explains the importance of cache coherence in multiprocessor systems, introducing the MESI protocol that maintains consistency among multiple caches. Additionally, it describes the various states of cache lines within the MESI protocol and how they manage data consistency during processor interactions.

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11 views39 pages

Module 5 - Pentium

The document provides an overview of Intel's Pentium processors, detailing their evolution from the original Pentium in 1993 to the Pentium 4, highlighting their architecture, features like MMX technology, and the advantages of superscalar processing. It also explains the importance of cache coherence in multiprocessor systems, introducing the MESI protocol that maintains consistency among multiple caches. Additionally, it describes the various states of cache lines within the MESI protocol and how they manage data consistency during processor interactions.

Uploaded by

8 11B Manasi kambli
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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• Intel made and sold the Pentium computer from 1993 to

the present.
• These processors are optimized for desktop and laptop
computers that are used a lot because they offer a good
balance between price and speed.
• Following Intel's previous 486 series, which offers faster
and more efficient computing, followed the Pentium
CPUs.
• Support cutting-edge capabilities such as MMX
technology, which improves multimedia and graphics
performance, and superscalar architecture, which
enables the processing of many instructions at once.
Generations of Pentium Processors
The five generations of Pentium processors are-
• Pentium (Original)

• Pentium Pro

• Pentium II

• Pentium III

• Pentium 4
Pentium (Original)

• The 1993 Pentium processor had the capacity to execute several


instructions per clock cycle.

• It revolutionized Intel's microprocessor technology.

• With 60 MHz and 66 MHz clock rates, 3.1 million transistors, and 32-bit
processing.

• It had 8 KB of data and instruction caches.

• It provided better performance than its predecessor, the 486, with


dual pipelines, that allow it to process two instructions simultaneously.
• The Pentium is a 32-bit processor, but it has a 32-bit address bus
and a 64-bit data bus.
• This processor’s data bus serves the on-chip caches, but not the 32-
bit registers.
• The internal and external data buses are connected through the
caches.
• Figure shows the internal architecture of Pentium processor which
consists of
• 8K byte code cache,
• 8K byte data cache,
• Translation Look-aside Buffer (TLB),
• Branch Target Buffer (BTB),
• Integer pipelines U and V,
• floating-point pipeline,
• Microcode ROM, and
• Code and Data Cache:
• There are separate code and data caches, and the
cache line size is 32 bits.
• Each cache is connected with its own Translation Look-
aside Buffer (TLB).
• Therefore, the paging unit of the Memory Management
Unit (MMU) can rapidly convert linear code or data
addresses into physical addresses.
• Due to two separate caches, the pre-fetches cannot
conflict with data access cycles.
• Branch Prediction:
• Branch prediction consists of a
• Control Unit (CU) and a
• Branch Trarget Buffer (BTB).
• The function of control unit and Branch target buffer are
as follows:
• Branch Target Buffer (BTB):
• The BTB is used to store the target address and
statistical information about the branch operation.
• Hence, the branch prediction is able to predict branches
and cause the Pentium to use the most likely target
address for instruction fetching.
• Pipeline freeze up caused by pipeline flushes and the
subsequent fetching operations are reduced and the
program execution is accelerated
• Control Unit (CU):
• The control unit controls the five-stage integer pipelines U and V,
and the eight-stage floating-point.
• In the Architecture of Pentium Processor, the integer pipelines are
used for all instructions which are not involved in any floating-
point operations.
• Therefore, the Pentium can transmit two integer instructions in the
same clock cycle and performance of the processor is improved.
• This method is called superscalar architecture.
• Figure shows the superscalar organization of the Pentium
processor.
• Each of this pipeline has 5 stages of execution
Pipelining of Pentium Microprocessor
Branch Prediction Logic
Cache Memory Organization
Cache Coherence in Multiprocessor Systems
Cache coherence is the mechanism that ensures consistency between
multiple caches in a multiprocessor system, where multiple processors
access and modify shared memory.
Why is Cache Coherence Important?
In multiprocessor systems, each processor has its own private cache to
reduce memory access latency. However, when multiple processors
modify shared data, inconsistencies can arise.
Example of Cache Inconsistency
1.P1 loads a variable X = 10 from memory into its cache.
2.P2 loads the same variable X = 10 into its cache.
3.P1 updates X = 20 in its cache, but P2 still has X = 10.
4.Memory and P2’s cache now hold an outdated value, leading to
incoherence.
Coherence vs. Consistency
• Cache Coherence ensures all copies of a memory location have the
same value.
• Memory Consistency defines the order in which memory updates
appear to processors.
• The MESI protocol (Modified, Exclusive, Shared, Invalid) is a cache
coherence protocol used in multiprocessor systems to ensure that multiple
caches maintain a consistent view of memory. It helps manage data
consistency when multiple processors access shared memory.
MESI States
Each cache line in a processor's cache can be in one of four states:
1.Modified (M): The cache line is dirty (modified only in this cache) and must
be written back to memory before another processor can use it.
2.Exclusive (E): The cache line is clean (matches main memory), but only this
cache has it.
3.Shared (S): The cache line is clean and may be in multiple caches.
4.Invalid (I): The cache line is stale (not valid) and must be reloaded from
memory.
• The protocol works by allowing caches to snoop on each other's bus
transactions.
• When a processor wants to read or write to a memory location, it
broadcasts its intention on the bus.
• Other caches then check their MESI states to determine if they have a
copy of the memory location and whether it needs to be invalidated,
updated, or shared.
• By using the MESI protocol, the system ensures that all caches have a
consistent view of memory, preventing issues such as data corruption or
inconsistency.

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