Module 3

Programmable peripheral
interface 8255
• PPI 8255 is a general purpose programmable I/O device
designed to interface the CPU with its outside world
such as ADC, DAC, keyboard etc. We can program it
according to the given condition. It can be used with
almost any microprocessor. It consists of three 8-bit
bidirectional I/O ports i.e. PORT A, PORT B and PORT C.
We can assign different ports as input or output
functions.
Pin Diagram
•PA0 – PA7 – Pins of port A
•PB0 – PB7 – Pins of port B
•PC0 – PC7 – Pins of port C
•D0 – D7 – Data pins for the transfer of data
•RESET – Reset input
•RD’ – Read input
•WR’ – Write input
•CS’ – Chip select
•A1 and A0 – Address pins
• It consists of 40 pins and operates in +5V regulated power supply.
• Port C is further divided into two 4-bit ports i.e. port C lower and
port C upper and port C can work in either BSR (bit set rest) mode
or in mode 0 of input-output mode of 8255.
• Port B can work in either mode 0 or in mode 1 of input-output mode.
• Port A can work either in mode 0, mode 1 or mode 2 of input-output
mode.
• It has two control groups,
control group A and control
group B. CS’ A1 A0 Selection Address

• Control group A consist of port

0 0 0 PORT A 80 H
A and port C upper.
• Control group B consists of port 0 0 1 PORT B 81 H

C lower and port B. 0 1 0 PORT C 82 H

• Depending upon the value if
CS’, A1 and A0 we can select 0 1 1
Control
Register
83 H
different ports in different
modes as input-output function
1 X X No Seletion X
or BSR.
• This is done by writing a
suitable word in control register
(control word D0-D7).
Operating Modes of 8255
• PPI 8255 can operate in three modes:
(a) Mode 0
(b) Mode 1 and
(c) Mode 2.
Apart from these there is another mode called BSR mode (Bit Set/Reset
mode)
The three modes are Mode 0, Mode 1 and Mode 2.
These are I/O operations and selected only if D7 bit of the control word
register is put as 1.
• The three ports are divided into two groups—Groups A and B. Group A consists of Port A
and CU ( PC4–PC7 ) . Port A can be operated in any of the modes—0, 1 or 2. Group B
consists of Port B and CL( PC0–PC3 ). Here Port B can be operated in either mode 0 or 1.
• The three operating modes of 8255 are distinguished in the following
manner:
• Mode 0: This is a basic or simple input/output mode, whose features are: ➢
Outputs are latched.
➢ Inputs are not latched.
➢ All ports (A, B, CU, CL) can be programmed in either input or output mode.
➢ Ports don’t have handshake or interrupt capability.
➢ Sixteen possible input/output configurations are possible.
• Mode 1:
• In this mode, input or output of data is carried out by taking the help of
handshaking signals, also known as strobe signals.
The basic features of this mode are:
➢ Ports A and B can function as 8-bit I/O ports, taking the help of pins of Port C.
➢ I/Ps and O/Ps are latched.
➢ Interrupt logic is supported.
➢ Handshake signals are exchanged between CPU and peripheral prior to data
transfer.
➢ In this mode, Port C is called status port.
➢ There are two groups in this mode—group A and group B. They can be
configured separately.
Each group consists of an 8-bit port and a 4-bit port. This 4-bit port is used for
handshaking in each group.
• BSR (Bit Set Reset mode):
• BSR mode stands for Bit Set Reset mode.
• The characteristics of BSR mode are:
➢ BSR mode is selected only when D7 = 0 of the Control Word
Register (CWR).
➢ It is concerned with bits of port C.
➢ Individual bits of Port C can either be Set or Reset.
➢ At a time, only a single bit of port C can be Set or Reset.
➢ Is used for control or on/off switch.
➢ BSR control word doesn’t affect ports A and B functioning.
8255 Interfacing with 8086:
• Fig. shows the 8255 Interfacing with 8086 Microprocessor and
Interfacing 8255 with 8086 Microprocessor in I/O mapped I/O
technique.
• Here RD and WR signals are activated when IO/M’ signal is high,
indicating I/O bus cycle.
• Reset out signal from 8086 is connected to the RESET signal of the
8255.
• Interfacing of
8255 in
I/O mapped I/O
• Fig. shows the interfacing of 8255 with 8086 in memory
mapped I/O technique. Here RD and WR signals are activated when
IO/M signal is low, indicating memory bus cycle.
• To get absolute address, all remaining address lines (A 15 – A2) are used
to decode the address for 8255. Other signal connections are same as
in I/O mapped I/O.
• Interfacing of
8255 in
memory mapped
I/O
 Direct memory access with DMA controller 8257
• Suppose any device which is connected to input-output port wants to
transfer data to memory, first of all it will send input-output port
address and control signal, input-output read to input-output
port, then it will send memory address and memory write signal to
memory where data has to be transferred.
• In normal input-output technique the processor becomes busy in
checking whether any input-output operation is completed or not
for next input-output operation, therefore this technique is slow.
• This problem of slow data transfer between input-output port and
memory or between two memory is avoided by implementing Direct
Memory Access (DMA) technique.
• This is faster as the microprocessor/computer is bypassed and the
control of address bus and data bus is given to the DMA controller.
• HOLD – hold signal

• HLDA – hold acknowledgment

• DREQ – DMA request

• DACK – DMA acknowledgment

• Suppose a floppy drive that is connected at input-output port wants to
transfer data to memory, the following steps are performed:

• Step-1: First of all the floppy drive will send a DMA request (DREQ)
to the DMAC, it means the floppy drive wants its DMA service.
• Step-2: Now the DMAC will send a HOLD signal to the CPU.
• Step-3: After accepting the DMA service request from the DMAC, the
CPU will send hold acknowledgment (HLDA) to the DMAC, it means
the microprocessor has released control of the address bus the data bus
to DMAC and the microprocessor/computer is bypassed during DMA
service.
• Step-4: Now the DMAC will send one acknowledgement (DACL) to
the floppy drive which is connected at the input-output port. It means
the DMAC tells the floppy drive be ready for its DMA service.

• Step-5: Now with the help of input-output read and memory write
signal the data is transferred from the floppy drive to the memory.
Modes of DMAC:
1. Single Mode – In this only one channel is used, means only a single
DMAC is connected to the bus system.
2. Cascade Mode – In this multiple channels are used, we can further
cascade more number of DMACs.
Advantages:

Improved performance: DMA improves system performance by freeing up the

CPU to perform other tasks while data is being transferred between memory and
I/O devices. This allows for faster and more efficient data transfer.

Reduced CPU overhead: With DMA, the CPU is not required to be involved in
data transfer, which reduces the CPU overhead and allows it to focus on other
tasks. This is particularly useful in real-time systems where low latency and fast
response times are important.

Support for high-bandwidth devices: DMA can support high-bandwidth devices

such as graphics cards and network interfaces that require fast data transfer rates.

Efficient use of system resources: DMA allows multiple devices to access

memory simultaneously, which makes more efficient use of system resources.
 8259 PIC Microcontroller

• Intel 8259 is a Programmable Interrupt Controller

(PIC).
• There are 2 hardware interrupts in Intel 8086
microprocessors respectively.
• But by connecting Intel 8259 with these
microprocessors, we can increase their interrupt
handling capability.
• Intel 8259 combines the multi-interrupt input sources
into a single interrupt output.
• Features of Intel 8259 PIC are as follows:
1.Intel 8259 is designed for Intel 8086
microprocessor.
2.It can be programmed either in level triggered or in
edge triggered interrupt level.
3.We can mask individual bits of interrupt request
register.
4.We can increase interrupt handling capability upto
64 interrupt level by cascading further 8259 PICs.
5.Clock cycle is not required.
Pin Diagram of 8259 – We can see through above diagram that there are total 28 pins in Intel
8259 PIC where Vcc : 5V Power supply and Gnd : ground. Other pins use are explained
below. Block Diagram of 8259 PIC microprocessor –
The Block Diagram consists of 8 blocks which are – Data Bus Buffer,
Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority
Resolver and 3 registers- ISR, IRR, IMR.
1.Data bus buffer – This Block is used as a mediator between 8259 and
8086 microprocessor by acting as a buffer. It takes the control word
from the 8086 microprocessor and transfer it to the control logic of
8259 microprocessor. After selection of Interrupt by 8259
microprocessor (based on priority of the interrupt), it transfer the opcode
of the selected Interrupt and address of the Interrupt service sub routine
to the other connected microprocessor. The data bus buffer consists of 8
bits represented as D0-D7 in the block diagram. Thus, shows that a
maximum of 8 bits data can be transferred at a time.

2.Read/Write logic – This block works only when the value of pin CS is
low (as this pin is active low). This block is responsible for the flow of
data depending upon the inputs of RD and WR. These two pins are
active low pins used for read and write operations.
1.Control logic – It is the center of the PIC and controls the functioning of
every block. It has pin INTR which is connected with other
microprocessor for taking interrupt request and pin INT for giving the
output.
If 8259 is enabled, and the other microprocessor Interrupt flag is high then
this causes the value of the output INT pin high and in this way 8259
responds to the request made by other microprocessor.
2.Interrupt request register (IRR) – It stores all the interrupt level which
are requesting for Interrupt services.
3.Interrupt service register (ISR) – It stores the interrupt level which are
currently being executed.
4.Interrupt mask register (IMR) – It stores the interrupt level which
have to be masked by storing the masking bits of the interrupt level.
1.Priority resolver – It examines all the three registers
and set the priority of interrupts and according to the
priority of the interrupts, interrupt with highest priority
is set in ISR register. Also, it reset the interrupt level
which is already been serviced in IRR.

2.Cascade buffer – To increase the Interrupt handling

capability, we can further cascade more number of pins
by using cascade buffer. So, during increment of
interrupt capability, CSA lines are used to control
multiple interrupt structure.
• SP/EN (Slave program/Enable buffer) pin is when set to
high, works in master mode else in slave mode. In Non
Buffered mode, SP/EN pin is used to specify whether
8259 work as master or slave and in Buffered mode,
SP/EN pin is used as an output to enable data bus.
• Interrupt Management: The 8259 PIC is designed to handle
interrupts efficiently and effectively, allowing for faster and
more reliable processing of interrupts in a system.
• Flexibility: The 8259 PIC is programmable, meaning that it can
be customized to suit the specific needs of a given system,
including the number and type of interrupts that need to be
managed.
• Compatibility: The 8259 PIC is compatible with a wide range
of microprocessors, making it a popular choice for managing
interrupts in many different systems.
• Multiple Interrupt Inputs: The 8259 PIC can manage up to 8
interrupt inputs, allowing for the management of complex
systems with multiple devices.
• Ease of Use: The 8259 PIC includes simple interface pins and
registers, making it relatively easy to use and program.
Operating modes of 8259 :

Fully nested mode :

• This is the normal mode of operation.
• Highest priority interrupt is always served first.
• If a higher-priority interrupt occurs during execution, it will preempt the
lower-priority one.
• Used in most general applications.
2. Automatic End of Interrupt (AEOI) Mode
• The End of Interrupt (EOI) signal is automatically sent after the CPU
acknowledges the interrupt.
• The CPU does not need to manually send an EOI command.
• Speeds up interrupt handling but does not allow nested interrupts
3. Specific End of Interrupt (EOI) Mode
• The CPU must explicitly send an EOI command after handling an interrupt.
• Used when software wants to control priority levels manually.
• More flexible but requires extra CPU instructions.
4. Special Fully Nested Mode
• Used in cascaded mode, where multiple 8259 PICs are connected.
• Allows higher-priority interrupts from a secondary PIC to override
those from the primary PIC.
5. Buffered Mode
• Used when the 8259 is connected in a system with bus buffering.
• The SP/EN (Slave Program/Enable) pin is used to select the active
8259.
• Can be used in master or slave configurations.
6. Polling Mode
• Instead of interrupts, the CPU polls (checks) the 8259 to see if an interrupt is
pending.
• Used in systems without interrupt lines or for debugging purposes.
• Slower than normal interrupt-based handling.
7. Cascade Mode
• Allows multiple 8259 controllers to be connected in a master-slave configuration.
• A master 8259 can handle up to 8 slave 8259s, expanding the interrupt lines to
64.
• Used in complex systems needing more interrupts
Specific Rotation Mode (Specific Priority Mode)
• Allows a specific IRQ to be set as the highest priority.
• Useful in systems where one interrupt source is more critical than
others.
Automatic Rotation Mode
• After servicing an interrupt, the next IRQ in sequence gets the highest
priority.
• Useful in round-robin scheduling scenarios, like multi-device polling.
Special Mask Mode
• Normally, lower-priority interrupts are blocked while a higher-priority
interrupt is being serviced.
• In Special Mask Mode, lower-priority interrupts can still be received
even while a higher-priority interrupt is active.
• Used in real-time applications where no interrupt should be
completely blocked.
Memory Interfacing
• When we are executing any instruction, we need the microprocessor to
access the memory for reading instruction codes and the data stored in
the memory.
• For this, both the memory and the microprocessor requires some
signals to read from and write to registers.
• The interfacing process includes some key factors to match with the
memory requirements and microprocessor signals.
• The interfacing circuit therefore should be designed in such a way that
it matches the memory signal requirements with the signals of the
microprocessor.
• A general form diagram of ROM and RAM show in figure (1).
• Pin connections common to all memory devices are:
• Address connections: All memory devices have address inputs that select

• Address inputs are labelled (𝐴0 − 𝐴𝑛)

a memory location within the memory device.

• Data connections: All memory devices have a set of data outputs or

input/outputs.
• Today many of them have bi-directional common I/O pins.
• Selection connections: Each memory device has an input that selects or
enables the memory device. This kind of input is most often called a chip
select (CS) , chip enable (CE) or simply select (S) input.
• Control connections: The control input most often found on the ROM is
the output enable (OE) or gate (G) this allows data to flow out of the
output data pins of the ROM.
Design 8086 microprocessor based system using minimum mode with following
specifications:
i) 8086 microprocessor working at 10 MHz. ii) 128 KB EPROM using 32 KB Chip iii) 64 KB
SRAM using 16 KB Chip.
1. Absolute Decoding :
• In absolute decoding technique the memory chip is selected only for the
specified logic level on the address lines; no other logic levels can
select the chip. Fig 10.12 shows the memory interface. with absolute
decoding. Two 8K EPROMs (2764) are used to provide even and odd
memory banks. Control signals BHE and A0 are used to enable outputs
of odd and even memory banks respectively. As each memory chip has
8K memory locations, thirteen address lines are required to address
each locations, independently. All remaining address lines are used to
generate an unique chip select signal. This addressing technique is
normally used in large, memory systems.
2.Linear Decoding or Partial Decoding. :
• In small systems, hardware for the decoding logic can be eliminated,by
using only required number of addressing lines (not all). Other lines are
simply ignored. This technique is referred as Linear Decoding or Partial
Decoding. 10.13 shows the addressing of 16K RAM (6264) with linear
decoding. Control signals BHE and A0 are used to, enable odd and even
memory banks, respectively. The address line A 19 is used to select the RAM
chips. When A19 is low, chip is selected, otherwise it is disabled. The status
of A14 to A18 does not affect the chip selection logic. This gives you multiple
addresses (shadow addresses). This technique reduces the cost of Address
Decoding Techniques in 8086 Microprocessor circuit, but it has drawback
of multiple addresses.
Aspect Absolute Decoding Partial Decoding
Address Lines Used All address lines Only some address lines
Hardware Complexity High Low
Multiple addresses can map to the
Address Uniqueness Unique address for each device
same device
Cost High Low
Risk of Interference No Yes