Chapter 2

Peripherals & Interfacing

• 8255-PPI
• 8279-KBDC
• ADC 0808, DAC 0808
• 8254-PIT
• 8259-PIC
• 8251-SCI
• 8257-DMAC

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8255-Programmable Peripheral Interface-PPI

• PPI 8255 is a general purpose programmable I/O

device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard,
Display etc.
• We can program it according to the given
condition. It can be used with almost any
microprocessor.
• It consists of three 8-bit bidirectional I/O ports i.e.
PORT A, PORT B and PORT C grouped to Group A &
Group B.
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3
• Data bus buffer: Tristate bidirectional buffer;It
is used to interface 8255 with the system bus
• Read/Write control logic: It accepts control
signals (RD, WR..) and issues commands to
Group A & Group B control blocks.
• Group A & Group B control blocks: Accept
control from CPU & issues command to the
ports

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The common applications of 8255 are:
• Traffic light control
• Generating square wave
• Interfacing with KB, Display, DC motors and stepper motors

To communicate with peripherals through 8255 three steps are necessary:

• Determine the addresses of Port A, B, C and Control register according to Chip
Select Logic and the Address lines A0 and A1.
• Write a control word in control register.
• Write I/O instructions to communicate with peripherals through port A, B, C.

Modes of operation of 8255:

Input/Output mode
• Mode 0: Simple I/O mode
• Mode 1: I/O mode with handshake
• Mode 2: Bidirectional data transfer mode
BSR mode (Bit Set/Reset mode) 5
Input/Output mode

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I/O Modes of 8255
Mode 0: Simple Input or Output
• In this mode, Port A and Port B are used as two simple 8-bit I/O ports and Port C as
two 4- bit I/O ports. Each port (or half-port, in case of Port C) can be programmed
to function as simply an input port or an output port.
• The input/output features in mode 0 are: Outputs are latched, Inputs are not
latched. Ports do not have handshake or interrupt capability.
Mode 1: Input or Output with handshake
• In mode 1, handshake signals are exchanged between the microprocessor and
peripherals prior to data transfer.
• The ports (A and B) function as 8-bit I/O ports. They can be configured either as
input or output ports. Each port (Port A and Port B) uses 3 lines from port C as
handshake signals. The remaining two lines of port C can be used for simple I/O
functions. Input and output data are latched and Interrupt logic/handshake facility
is supported.
• Mode 2: Bidirectional Data Transfer
• This mode is used primarily in applications such as data transfer between the two
computers or floppy disk controller interface. Port A can be configured as the
bidirectional port and Port B either in mode 0 or mode 1.
• Port A uses five signals from Port C as handshake signals for data transfer. The
remaining three lines from Port C can either as simple I/O or as handshake signals
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for Port B.
8251-USART (Universal Synchronous
Asynchronous Receiver Transmitter)

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• Programmable chip designed for synchronous
& asynchronous serial data transmission
• Converts parallel data into serial stream of bits
suitable for serial transmission
• Receives serial stream of bits & convert into
parallel data bytes to be read by
microprocessor

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Modem control:
• It handles the modem handshake signals to coordinate the
communication between the modem and USART.
• It establishes data communication through modem over telephone
lines
• DSR!: To check if the data set is ready when communicating with a
modem. Its status is checked by CPU using a status read operation
• DTR!: To indicate that the device is ready to accept data when the
8251 is communicating with a modem
• RTS!: To indicate the modem that the receiver is ready to receive a
data byte from the modem. This is used to communicate with a
modem.
• CTS!: If this is low, the 8251 is enabled to transmit the serial data.
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Operating Modes of 8251
1. Asynchronous mode
2. Synchronous mode
Two types of control words:
• Mode Instruction control word: Mode instruction is used for setting the function
of the 8251.
• Command Instruction control word: Command is used for setting the operation of
the 8251. It is possible to write a command whenever necessary after writing a
mode instruction and sync characters.

Mode instruction format-Asynchronous. 17

1: External Synchronization
0: Internal Synchronization
Synchronous - mode Instruction format

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It is possible to see the internal status of the 8251 by reading a status word.
The bit configuration of status word is shown in Fig.

Status information

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8254-Programmable Interval Timer/Counter

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• Generates accurate time delay
• Performs event counting, square wave generator
• Has 3 independent 16 bit presettable down counters (BCD or hexadecimal)
• It has 3 counters each with two inputs (Clock and Gate) and one output. Gate is
used to enable or disable counting. When any value of count is loaded and
value of gate is set (1), after every clock, value of count is decremented by 1
until it becomes zero.
Depending upon the value of CS, A1 and A0 we can determine addresses of
selected counter.
• Data is transmitted or received by the buffer on executing IN or OUT instructions
• The read/write logic controls the direction of the data buffer depending upon
whether it is a read or a write operation
• 8253can operate in any one of the six different modes. A control word must be
written in the respective control word register by the microprocessor to
initialize each of the counters of 8254 to decide its operating mode. All the
counters can operate in any one of the modes or they may be even in different
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modes of operation, at a time.
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• Mode 0 (Interrupt on terminal count)
• Mode 1 (Programmable one shot)
• Mode 2 (Rate generator)
• Mode 3 (Square wave generator)
• Mode 4 (Software triggered strobe)
• Mode 5 (Hardware triggered strobe)

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• Mode 0: Interrupt on TC:
• The output is initially low after the mode is set. The output
remains low even the count is loaded into the counter.
• After the falling edge of the clock, counter starts
decrementing the count value, if the GATE input is high.
• The counting process continues till the TC is reached. When
the TC is reached, OUT goes high & remains HIGH till the
count register is reloaded with a new mode or a new count.
• The high OUT can be used to interrupt the processor.
• When the GATE goes low, counting is terminated & the
current count is latched till the GATE goes high again.
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Mode 1: Programmable one shot:
• Used as monostable multivibrator
• The GATE input is used as trigger input
• Initially output remains high till the count is
loaded into the count register and a trigger is
applied. After the application of positive edge
trigger (GATE), output goes low and remains
low till the count becomes zero.

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Mode 2: Rate generator:
• Rate generator or divide by N counter
• If N=4 is loaded into the counter, after 4
pulses, the output becomes low only for one
clock cycle. Count N is reloaded again and
again.

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31
Mode 3: Square wave generator:
• Used as a Square wave generator
• If the count N is even, then for half of the count
(N/2 pulses) the output remains high and for
remaining N/2 pulses it remains low.
• If the count N is odd, then for (N+1)/2 pulses,
output remains high & for (N-1)/2 pulses,
output remains low. It is repeated to generate
square wave.
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Mode 4: Software Triggered Strobe:
• After the mode is set, the output goes high.
When a count is loaded, counting down starts.
On TC, the output goes low for one clock cycle
& then goes high. This low pulse can be used
as a strobe, when peripherals are interfaced
with microprocessor.
• When the GATE goes low, count is inhibited &
the count value is latched.
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Mode 5: Hardware Triggered Strobe:
• Initially the OUT is high. The counting is triggered by
the rising edge of the GATE. When initial count is
expired the OUT becomes low for one clock pulse, then
high again. After writing the control word and the
initial count, the counter will not be loaded until clock
pulse after one trigger.

In Software triggered strobe mode, the trigger is given

internally by the software whereas in hardware
triggered mode the trigger has to be given externally
by hardware. 36
37
8279 Programmable Keyboard/Display Controller

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 It consists 4 main sections:
1. CPU interface and control section.
2. Scan section
3. Keyboard Section
4. Display section.

 CPU INTERFACE AND CONTROL SECTION:

It consists of
1. Data buffers
2. I/O control
3. Control and timing registers.
4. Timing and control logic. 39
Data Buffers:
 8-bit bidirectional buffer.
 Used to connect the internal data bus and external data bus.
I/O control:
 I/O control section uses the A0,CS!,RD! and WR! signals to
controls the data flow.
 The data flow is enabled by CS!=0 otherwise it is the high
impedance state.
 A0=0 means the data is transferred.
 A0=1 means status or command word is transferred.

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 I/O control signals listed below

TIMING AND CONTROL REGISTERS:

 Store the keyboard and display modes and others operating condition
programmed by the CPU.
 The modes are programmed by sending proper command A 0=1.

TIMING AND CONTROL:

 It consists of timing counter
 First counter is divided by N prescalar that can be programmed to give an
internal frequency of 100 KHz.
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Scan Section
 It has two modes:
1. Encoded mode
2. Decoded mode.

ENCODED MODE:
 It is externally decoded to provide 16 scan lines
 It provides binary count from 0000 to 1111 by four
scan lines(SC3-SC0) by active high inputs.
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 Display section uses all 16 scan lines to interface 16 digit 7
segment display. These 16 scan lines are connected to the digit
drivers.
 But keyboard use only 8 scan lines out of 16 lines. These 8 scan
lines are connected to 8 rows of the KB. So 8*8 KB can be
interfaced.

DECODED MODE:
 In this mode, the internal decoder decodes the least 2 significant
bits & It provides four possible combination from (SL0-SL3)
 This four active low outputs line is used to directly to interface 4
–digit 7-segment display, 8*4 matrix keyboard
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Keyboard section
This is consist of
 Return buffers.
 Keyboard debounce control.
 FIFO / sensor RAM.
 FIFO / sensor RAM status.

RETURN BUFFERS:
 8 return lines (RL7-RL0) are connected to the 8 columns of the
keyboard.
 In strobed mode ,the contents of return lines are transferred to
FIFO RAM.
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KEYBOARD DEBOUNCE AND CONTROL:
 It is enabled only when keyboard mode is selected.
 In this mode , return lines are scanned whether any keys are
closed in the row.
 If debounce circuit detects any closed switch, it waits about
10 msec.
 It is continued , the key code along with the status of SHIFT
and CONTROL keys are transferred into RAM.

FIFO/SENSOR RAM:
 This is a dual function of 8*8 RAM.
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 The 8279 generates an interrupt signal when
there is an entry in FIFO.
 Each new entry is written into successive RAM
position and read in the order of entry.

FIFO/SENSOR RAM status:

 This is used to tell the status of FIFO/SENSOR RAM.
 The status of logic also makes IRQ signal is High ,
When FIFO is empty.

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Display section:
It consists of
1. Display RAM.
2. Display Address registers.
3. Display registers.
DISPLAY RAM:
 It is a 16*8 RAM.
 Which stores 16 digits display codes.
 It can be accessed by CPU directly. 47
DISPLAY ADDRESS REGISTERS:
 Used to hold address of the byte currently written or
read by the CPU and scan count value.
 In auto increment mode, address in the register is
automatically incremented for each write or read.
DISPLAY REGISTERS:
 Two 4-bit registers such as A and B.
 They hold the bit patterns of character to be displayed.
 The content of display registers A and B can be blanked
and inhibited individually during digit switching (BD!).
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Operating modes
1. Input modes.
2. Display modes.
INPUT MODES:
 It is basically 3 types,
1. Scanned keyboard.
2. Scanned sensor matrix.
3. Strobed mode.

SCANNED KEYBOARD:
Key board can be scanned in two ways.
1.Encoded Scan
2.Decoded Scan.
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ENCODED SCAN:
 In this scan, scan lines (SL2-SL0) are decoded externally
to provide 8 scan lines.
 Additionally it provides 8 return lines.
 So the size of matrix keyboard is 8*8 (i.e Scan *
Return)=64.
 When the key is pressed , it stores the status of return
lines, Scan lines, SHIFT and CNTL/STB keys into FIFO
RAM.
 The Scanned keyboard structure is

DECODED SCAN:
In this mode, internal decoder decodes the two least significant bits of scan
lines (SL3-SL0).
So the maximum size of keyboard is 8*4=32.
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2-KEY LOCKOUT:
 In this mode, the two key depression is not
allowed.
 When two keys are depressed almost at the
same time, the first key will be detected,
debounced & decoded. Then the status of key
code is entered into FIFO RAM along with the
status of CNTL and SHIFT lines.
 Second key press will be missed.
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N-KEY ROLLOVER:
 Each key is recognized, debounced & detected
independently from all others.
 All the pressed keys will be detected,
debounced & decoded independently.

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Display modes:
It is basically two types
1. Left entry (Type writer mode).
2. Right entry (Calculator mode).
LEFT ENTRY:
 In this mode , 8279 display characters from left to right.
 Like a typewriter.
AUTO INCREMENT IN LEFT ENTRY:
 In left entry mode , Auto increment flag is set; after
each operation, display RAM address is incremented.
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RIGHT ENTRY:
 In this mode , 8279 display characters from
Right to left.
 Like a Calculator.
AUTO INCREMENT IN RIGHT ENTRY:
 In right entry mode, Auto increment flag is
set; after each operation display RAM
address is incremented.
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8259-Programmable Interrupt Controller

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The Interrupt Request Register (IRR):
An 8-bit register in which the active interrupt requests are stored. Whenever
activation of an interrupt request input is done, the bit corresponding in IRR
register is set to 1. For example, if we activate the IR4 and IR6 inputs, bits no 4
and 6 of IRR are set to 1 by making the contents of IRR as 01010000. But the
processor is designed only to read the contents of this register but cannot
write it to IRR.
The interrupt Mask Register (IMR):
• This register is used to disable (mask) or enable (unmask) individual
interrupt inputs. Each bit in this register corresponds to the interrupt input
with the same number. We can unmask an interrupt input by sending a
command word with a 0 in the bit position that corresponds to that input.
The In Service Register (ISR):
• The ISR keeps track of which interrupt inputs are currently being serviced.
For each input that is currently being serviced, the corresponding bit will be
set in the ISR.
The Priority Resolver:
It examines all the three registers and set the priority of interrupts and
according to the priority of the interrupts, interrupt with highest priority is
selected for service. Hence it sets an appropriate bit in ISR register. Also, it 56
resets the interrupt level which is already been serviced in IRR.
Interrupt Sequence in 8086:
1. One or more of the INTERRUPT REQUEST lines are raised high, setting the
corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.
3. The CPU acknowledges the INT and responds with an INTA! pulse.
4. Upon receiving an INTA! from the CPU, the highest priority ISR bit is set,
and the corresponding IRR bit is reset. The 8259A will also release a CALL
instruction code onto the 8-bit Data Bus through its Data pins.
5. This CALL instruction will initiate two more INTA! pulses to be sent to the
8259A from the CPU.
6. These two INTA! pulses allow the 8259A to release its 16 bit subroutine
address onto the Data Bus. The lower 8-bit address is released at the first
INTA! pulse and the higher 8-bit address is released at the second INTA!
pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the
AEOI mode, the ISR bit is reset at the end of the third INTA! pulse.
Otherwise, the ISR bit remains set until an appropriate EOI command is
issued at the end of the interrupt subroutine.
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8259A Interrupt Operation:
• To implement interrupt, the interrupt enable flip-flop in the
microprocessor should be set by writing the EI instruction and
the 8259A should be initialized by writing control words in the
control register.
• The 8259A requires two types of control words:
(a) Initialization Command Words (ICWS)
(b) Operational Command Words (OCWs)
• ICWs are used to initialize & to set up the proper conditions and
specify RST vector address.
• The OCWs are used to perform functions such as masking
interrupts, setting up status-read operations etc.
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Initialization Command Words (ICWs):
• There are four initialization command words (ICWs) for the 8259A that
are selected when A0 pin is logic one. If a single 8259A is used in a
system, ICW1, ICW2, ICW3 and ICW4 must be programmed.
• If cascade mode is used in a system, then all four ICWs must be
programmed.
• ICW1: Programs the basic operation of 8259A. To program this ICW for
8086-Pentium 4 operation, place a logic 1 in bit IC4. Bits ADI, A7, A6,
A5 are don’t care for microprocessor operation and only apply to the
8259A when used with an 8-bit 8085 microprocessor.
• This ICW1 selects single or cascade operation by programming the
SNGL bit. The LTIM bit determines whether the interrupt request
inputs are positive edge-triggered or level-triggered.

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60
61
Operation Command Words (OCWs):
• Once 8259 is initialized, it is ready for
processing interrupts. The operational
command words (OCWs) are used to direct
the operation of the 8259A in desired mode
once it is programmed with ICW.
• 3 OCWS: OCW1, OCW2 & OCW3 are needed
to operate 8259 in the initialized mode.

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 ADC interfacing
• ADC is an input device to microprocessor & is interfaced
with microprocessor using ports of 8255.
• 2 ADC techniques: Successive approximation
& dual slope integration techniques
Algorithm:
1. Apply stable analog input to ADC using Sample & Hold
circuit
2. Apply SOC (Start Of Conversion) pulse by microprocessor
to the ADC
3. Read EOC (End Of Conversion) pulse by microprocessor
4. Read digital data output of ADC by the microprocessor
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ADC interfacing

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Features:
• Internal circuits perform zero & full scale adjustment
• Conversion time: 100microsec
• 8 channels; one can be selected using address lines
(Select lines) A, B & C.
• Unipolar ADCs; able to convert only negative analog
voltage to their equivalent digital
• 8 bit successive approximation ADC
• Eliminates need for external zero & full scale
adjustment
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• Clock input is given
• Port A of 8255 is used to transfer digital data of ADC to 8086
& Port C is used to transfer control signals
• Analog input is given to I/P2 of ADC
• Through Port B, 8086 sends select signals (ABC), to select I/P2
• ABC=010 to select I/P2 of ADC
• OE & ALE pins are kept at +5V to select ADC & enable the
outputs
• PC lower acts as output port to send SOC to ADC;
PC upper receives EOC

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Interfacing ADC0808 with 8086

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DAC 0800 interfacing

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• When DAC is enabled, it converts digital input
given through PA to analog
• The analog output from DAC is current
• It is converted to voltage using OP-AMP based
I to V converter
• The output of DAC is fed to OP-AMP to get the
final output.

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8257 DMAC(DMA Controller)

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Features of 8257
• It has four channels which can be exhibited over four I/O
devices.
• Each channel has 16-bit address and 14-bit counter registers
• Data transfer of each channel can be taken up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform certain specific actions i.e, DMA
read, DMA write and DMA verify operations.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.

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• The DMA controller in a sense is a second processor in the
system but is dedicated to an I/O function
• DMA Channels: 8257 has 4 independent DMA channels (CH0 to
CH3), hence four I/O devices can request for DMA
simultaneously.
• Each channel consists of two 16-bit registers:
(i) Address register (ii) Count Register.
• Address register holds the starting address of the memory block
to be accessed by I/O device.
• Count register holds the number of bytes to be transferred
during DMA action.
• The low order 14-bits of count register specify the number of
bytes; therefore each channel can support data transfer of
214=16KB during DMA process.
• The high order 2-bits of count register specify the mode of
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operation (read, write or verify)
• Data Bus Buffer: This 8-bit Bidirectional buffer is
used to interface the 8257 to the system Data Bus.
It allows the transfer of data and information
between 8257 and microprocessor.
• Read/Write Control Logic: 8257 operates in two
basic modes, master mode and slave mode. In the
slave mode, read/write logic accepts the or signal.
In the master mode, read/write logic generates
and for DMA write cycle or and for DMA read
cycle.
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• Priority Resolver: This logic block determines the priorities of
the channels when more than one I/O device request for DMA.
By default CH0 has the highest priority while the CH3 has
lowest. In rotating priority, the priority of the channels has a
circular sequence. The channel which has being just serviced
move to the lowest priority and channel next to it move to the
highest priority, hence each channel achieves the highest
priority in rotation.
• Control Logic: In the master mode, Control logic controls the
sequence of operation during DMA cycles (DMA read, DMA
write & DMA verify). It also generates required control signals
and memory address to be accessed.
• It increments 16-bit address register and decrement count
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register of corresponding channel during DMA action.
Sequence of operations performed by a DMA :

• Primarily, when any device requires to send data between the device
and the memory, the device need to send DMA request (DRQ) to
DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits
for the CPU to assert the HLDA signal.
• Then the microprocessor tri-states all the data bus, address bus, and
control bus. The CPU leaves the control over bus and acknowledges
the HOLD request through HLDA signal.
• when the CPU is in HOLD state with the HOLD request, the DMA
controller has to control the operations over buses between the CPU,
memory, and I/O devices.
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