ONLINE CLASS (2021-22)

PROGRAMMING IN HDL(SECA1605)

MENTORS
Dr.T.VINO
Mr.Muthiah
Department of ECE
Sathyabama Institute of Science and Technology
SYLLABUS
Course Outcome
After the completion of course student will be able to

CO1 Understand the requirements of VHDL design flow

CO2 Interpret the Verilog language elements and its relevance to
digital design
CO3 Apply the Modelling Styles for Simulation, Synthesis and
Test Bench Creation.
CO4 Analyse the Performance Study of Combinational and
Sequential logic design using Verilog
CO5 Evaluate State Machine and Memory designs by Verilog
CO6 Create and realize the system in FPGA using Verilog
FEATURES IN VERILOG HDL
Task and Functions
FEATURES IN VERILOG HDL
Differences between Functions and Tasks
FEATURES IN VERILOG HDL
Both Fucntions and Tasks

• Functions and Tasks are defined in a module

• Can have local variables (registers, but not nets) and
events contain only behavioral statements
• Do not contain initial or always statements but called from
initial or always statements or other tasks or functions

• Tasks can be used for common Verilog code

• Functions are typically used for conversions and
commonly used calculations
FEATURES IN VERILOG HDL
Tasks
Keywords: task, endtask
Must be used if the procedure has any timing control constructs
Zero or more than one output arguments
May be one or more input arguments

Task declaration and invocation

Task Declaration syntax

task <task_name>; <I/O declarations> <variable and event declarations>
begin
<statement(s)>
end
endtask

Task invocation syntax

<task_name>; <task_name> (<arguments>);
FEATURES IN VERILOG HDL
Tasks
Example
module simple_task();
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32)
end
endtask
endmodule
FEATURES IN VERILOG HDL
Functions
Keyword: function, endfunction
Can be used if the procedure does not have any timing control constructs
Returns exactly a single value
Has at least one input argument

Function Rules
Functions are more limited than tasks.
The following five rules govern their usage:
• A function definition cannot contain any time controlled statements—that is,
any statements introduced with #, @, or wait.
• Functions cannot enable tasks.
• A function definition must contain at least one input argument.
• A function definition must include an assignment of the function result value to
the internal variable that has the same name as the function.
• A function definition can’t contain an inout declaration or an output declaration
FEATURES IN VERILOG HDL
Function Declaration and Invocation
Declaration syntax:
function <range_or_type> <func_name>;
<input declaration(s)>
<variable_declaration(s)>
begin
<statements>
end
endfunction
Invocation syntax:
<func_name> (<argument(s)>);
Example
module simple_function();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
endmodule
FEATURES IN VERILOG HDL
SYSTEM TASKS AND FUNCTIONS
Verilog contains the pre-defined system tasks and functions, including tasks for
creating output from a simulation. All system tasks appear in the
form $.Operations such as displaying the screen, monitoring values of nets,
stopping and finishing are done by system tasks.

DISPLAY TASKS
$display
$monitor
$write

FILE I/O TASKS

$fclose
$fopen
$fdisplay
$readmemb

SIMULATION CONTROL TASKS

$finish
$stop
FEATURES IN VERILOG HDL
Modeling a Test bench
Test benches are used to test the RTL (Register-transfer logic) that we implement
using HDL languages like Verilog and VHDL.
Verifying complex digital systems after implementing the hardware is not a wise
choice. It is ineffective in terms of time, money, and resources. Hence, it is essential
to verify any design before finalizing it. Luckily, in the case of FPGA and Verilog, we
can use test benches for testing Verilog source code.

Design Under Test (DUT)

It is the circuit design that we would like to test. We can describe our DUT using one
of the three modeling styles in Verilog – Gate-level, Dataflow, or Behavioral.
For example,
module and_gate(c,a,b);
input a,b;
output c;
assign c = a & b;
endmodule

This AND gate can be our DUT in dataflow model.

FEATURES IN VERILOG HDL
Implementation of test bench
Consider the AND module as the design we want to test.
module and_gate_test_bench;

reg and wire declarations

reg A, B;
wire C;

DUT Instantiation
<dut_module> <instancename>(.<dut_signal>(test_module_signal),…)
and_gate dut(.a(A), .b(B), .c(C));

Applying the Stimulus

#5 A =0; B=0;
#5 A =0; B=1;
#5 A =1; B=0;
#5 A =1; B=1;
FEATURES IN VERILOG HDL
Test bench for AND Gate

module and_tb;
reg A,B;
wire C;
and_gate dut(.a(A), .b(B), .c(C));
initial
begin
#5 A =0; B=0;
#5 A =0; B=1;
#5 A =1; B=0;
#5 A =1; B=1;
end
end module
FEATURES IN VERILOG HDL
Testbench for D-flip flop

Let’s test the Verilog code for D-flip flop. Here’s the DUT:

module dff_behave(clk,rst,d,q,qbar);
input clk,rst,d;
output reg q,qbar;
always@(posedge clk)
begin
if (rst == 1)
q = 0;qbar = 1;
else
q = d;
qbar = ~d;
end
endmodule
FEATURES IN VERILOG HDL
Testbench for D-flip flop

module dff_tb;
reg CLK = 0;
reg D,RST;
wire Q,QBAR;
dff_behave dut(.clk(CLK), .rst(RST), .d(D), .q(Q), .qbar(QBAR));
always #10 CLK = ~CLK;
initial
begin
RST = 1;
#10 RST = 0;
#10 D = 0;
#20 D = 1
end
endmodule
FEATURES IN VERILOG HDL
Test Bench for Half Adder

module half_adder_verilog_tb;
reg a, b;
wire s, c;
halfadder8 dut (.a(a), .b(b), .s(s), .c(c));
initial
begin
a = 0;b = 0;
#50;a = 0;b = 1;
#50;a = 1;b = 0;
#50;a = 1;b = 1;
end
endmodule
FEATURES IN VERILOG HDL
Timing and Delays in Verilog
The concepts of timing and delays within circuit simulations are very important because
they allow a degree of realism to be incorporated into the modelling process

Delays
Delays can be modelled in a variety of ways, depending on the overall design approach
that has been adopted. namely gate-level modelling, dataflow modelling and behavioural
modelling.

Gate level modeling

Rise delay
The rise delay is associated with a gate output transition to a 1 from another value.
FEATURES IN VERILOG HDL
Fall delay
The fall delay is associated with a gate output transition to a 0 from another value.

Turn-off delay
The turn-off delay is associated with a gate output transition to the high impedance value
(z) from another value.

Example Program
module multiplexor_2_to_1(out, cnt, a, b);
output out;
input cnt, a, b;
wire not_cnt, a0_out, a1_out;
not # 2 n0(not_cnt, cnt); /* Rise=2, Fall=2, Turn-Off=2 */
and #(2,3) a0(a0_out, a, not_cnt); /* Rise=2, Fall=3, Turn-Off=2 */
and #(2,3) a1(a1_out, b, cnt);
or #(3,2) o0(out, a0_out, a1_out); /* Rise=3, Fall=2, Turn-Off=2 */
endmodule
FEATURES IN VERILOG HDL
Dataflow modelling
Net Declaration Delay
The delay to be attributed to a net can be associated when the net is declared.
e.g.
wire #10 out;
assign out = in1 & in2;

Regular Assignment Delay

This is used to introduce a delay onto a net that has already been declared.
e.g.
wire out;
assign #10 out = in1 & in2;

Implicit Continuous Assigment

Since a net can be implicitly assigned a value at its declaration, it is possible to introduce
a delay then, before that assignment takes place.
e.g.
wire #10 out = in1 & in2;
FEATURES IN VERILOG HDL
Behavioural modelling

Regular Delay or Inter-assignment delay

This is the most common delay used - sometimes also referred to as inter-assignment
delay control.
Example: #10 q = x + y;

Intra-Assignment Delay Control

With this kind of delay, the value of x + y is stored at the time that the assignment is
executed, but this value is not assigned to q until after the delay period, regardless of
whether or not x or y have changed during that time.
Example: q = #10 x + y;

Timing controls
Timing controls provide a way to specify the simulation time at which procedural
statements will execute.
There are three methods of timing control:
Delay based timing control
Event based timing control
Level-sensitive timing control
FEATURES IN VERILOG HDL
Delay-based timing control
There are three types of delay control for procedural assignments
Regular delay control
Intra-assignment delay control
Zero delay control

Regular delay control

Regular delay control is used when a non-zero delay is specified to the left of a
procedural assignment.

Example:
module clk_gen;
reg clk, reset;
clk = 0;
reset = 0;
#2 reset = 1;
#5 reset = 0;
#10 $finish;
endmodule
FEATURES IN VERILOG HDL
Intra-assignment delay control
Instead of specifying delay control to the left of the assignment, it is possible
to assign a delay to the right of the assignment operator
Example:
module intra_assign;
reg a, b;
a = 1;
b = 0;
a = #10 0;
b = a;
endmodule

Event based timing control

There are four types of event-based timing control
•Regular event control
•Named event control
•Event OR control
•Level-sensitive timing control
FEATURES IN VERILOG HDL
Regular event control
The @ symbol is used to specify an event control. Statements can be
executed on changes in signal value or at a positive or negative transition of
the signal value. The keyword posedge is used for a negative transition

Example:
module edge_wait_example();
reg enable, clk, trigger;
always @ (posedge enable)
begin
trigger = 0;
// Wait for 5 clock cycles
repeat (5)
begin
@ (posedge clk) ;
end
trigger = 1;
end
endmodule
FEATURES IN VERILOG HDL
Named event control
Verilog provides the capability to declare an event and then trigger and recognize the
occurrence of that event. A named event is declared by the keyword event. The
triggering of the event is recognized by the symbol @

Event OR control
The list of events or signals expressed as an OR is also known as a sensitivity list. The
keyword or is used to specify multiple triggers
Example:
always @(reset or clock or d)

Level-Sensitive Timing Control

Verilog allows a level-sensitive timing control, that is, the ability to wait for a certain
condition to be true before a statement or a block of statements is executed.
Example:
always
wait (count_enable) #20 count=count+1;
FEATURES IN VERILOG HDL
Switch Level Modeling
Usually, transistor level modeling is referred to model in hardware structures
using transistor models with analog input and output signal values.
On the other hand, gate level modeling refers to modeling hardware structures
with digital input and output signal values between these two modeling
schemes is referred to as switch level modeling.

At the switch level, transistors behave as on-off switches - Verilog uses a 4 value logic
value system, so Verilog switch input and output signals can take any of the four
0, 1, Z, and X logic values.

MOS switches
FEATURES IN VERILOG HDL
NMOS and PMOS Switches

In Verilog nmos and pmos switches are instantiated as shown in below,

nmos n1(out, data, control); // instantiate a nmos switch
pmos p1(out, data, control); // instantiate a pmos switch

Since switches are Verilog primitives, like logic gates, the name of the instance is
optional. Therefore, it is acceptable to instantiate a switch without assigning an instance
name.
nmos (out, data , control); // instantiate nmos switch ; no instance name
pmos (out, data, control); // instantiate pmos switch; no instance name
FEATURES IN VERILOG HDL
CMOS Switches

A CMOS switch is instantiated as shown in below,

cmos cl(out, data, ncontrol, pcontrol); //instantiate cmos gate

or
cmos (out, data, ncontrol, pcontrol); //no instance name given

The ncontrol and pcontrol are normally complements of each other.

When the ncontrol signal is 1 and pcontrol signal is 0, the switch conducts.

nmos (out, data, ncontrol); //instantiate a nmos switch

pmos (out, data, pcontrol); //instantiate a pmos switch

Since a cmos switch is derived from nmos and pmos switches, it is possible derive the
output value from Table, given values of data, ncontrol, and pcontrol signals.
FEATURES IN VERILOG HDL
Bidirectional Switches

NMOS, PMOS and CMOS gates conduct from drain to source.

But it is important to have devices that conduct in both directions.
In such cases, signals on either side of the device can be the driver signal.
Bidirectional switches are provided for this purpose.
FEATURES IN VERILOG HDL
Bidirectional Switches

Three keywords are used to define bidirectional switches: tran, tranif0, and tranifl.

The tran switch acts as a buffer between the two signals inoutl1and inout2.
Either inout1 or inout2 can be the driver signal.

The tranif0 switch connects the two signals inoutl1 and inout2 only if the control signal is
logical 0.
If the control signal is a logical 1, the non driver signal gets a high impedance value z.
The driver signal retains value from its driver.

The tranifl switch conducts if the control signal is a logical 1.

These switches are instantiated as shown in below

tran tl(inoutl, inout2); //instance name tl is optional
tranifO (inoutl, inout2, control); //instance name is not specified
FEATURES IN VERILOG HDL
Example-CMOS NAND

module my_nand (Out,A,B);

input A,B;
ouput Out;
wire C;
supply1 Vdd;
supply0 Vss;
pmos (Out,A,Vdd)
pmos (Out,B,Vdd);
nmos (Out,A,C);
nmos(C,Vss,B);
endmodule
 State Machine Modeling

Moore FSM Melay FSM

 Moore FSM
module moorefsm(a,clk,z); st1:
input a; begin
input clk; z=0;
output z; if(a)
reg z; moore_state=st3;
parameter st0=0,st1=1,st2=2,st3=3; end
reg[0:1]moore_state; st2:
initial begin
begin z=0;
moore_state=st0; if(~a)
end moore_state=st1;
else
always @ (posedge(clk)) moore_state=st3;
case(moore_state) end
st0: st3:
begin begin
z=1; z=1;
if(a) if(a)
moore_state=st2; moore_state=st0;
end end
endcase
endmodule
 Melay FSM
module mealayfsm(a, clk, z);
st1:
input a;
begin
input clk;
if(a) begin
output z;
z=0;
reg z;
mealy_state=st0;
parameter
end
st0=0,st1=1,st2=2,st3=3;
else
reg[0:1]mealy_state;
z=1;
initial
end st3:
begin
st2: begin
mealy_state=st0;
begin z=0;
end
if(a) begin if(a) begin
always @ (posedge(clk))
z=1; mealy_state=st1;
case(mealy_state)
mealy_state=st1; end
st0:
end else
begin
else mealy_state=st2;
if(a) begin z=0; end
z=1; end endcase
mealy_state=st3; end endmodule
else
z=0;
end
 DESIGN OF MEMORIES

ROM RAM
 ROM
module rom(addr, data_out);
input [2:0] addr;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0]mem [0:7];
initial
begin
mem[0]=8'b00000000;
mem[1]=8'b00000010;
mem[2]=8'b00000100;
mem[3]=8'b00001000;
mem[4]=8'b00010000;
mem[5]=8'b00100000;
mem[6]=8'b01000000;
mem[7]=8'b10000000;
end
always@(addr) begin
data_out=mem[addr];
end
endmodule
 RAM
module ram(clk, wr_en, data_in, addr, data_out);
input clk;
input wr_en;
input [7:0] data_in;
input [3:0] addr;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0]mem [0:15];

always@(posedge(clk),wr_en,data_in,addr)
if(clk)
begin
if(wr_en)
mem[addr]=data_in;
else
data_out=mem[addr];
end
endmodule