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Operating Modes

The document discusses the configuration of 8086 and 8088 microprocessors in minimum and maximum modes. Minimum mode is suited for smaller systems with a single microprocessor, while maximum mode supports larger systems with multiple processors. It also details bus timing, read and write operations, and the unique signals associated with each mode.

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Sampada Patil
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4 views20 pages

Operating Modes

The document discusses the configuration of 8086 and 8088 microprocessors in minimum and maximum modes. Minimum mode is suited for smaller systems with a single microprocessor, while maximum mode supports larger systems with multiple processors. It also details bus timing, read and write operations, and the unique signals associated with each mode.

Uploaded by

Sampada Patil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Minimum-mode and Maximum-

mode Systems
 8088 and 8086 microprocessors can be configured
 to work in either of the two modes: the minimum
 mode and the maximum mode

• Minimum mode:
 – Pull MN/MX to logic 1
 – Typically smaller systems and contains a single
microprocessor

• Maximum mode
 – Pull MN/MX logic 0
 – Larger systems with more than one processor
Minimum mode unique
signals
8086 Minimum-mode block
diagram
BASIC 8086 MINIMUM MODE SYSTEM

MN/
CLK MXM/IO
8284A
READY
CLOCK INTA
RESET
GENE-
RD
RATOR
WR
8282
DT/R
LATCH
DEN
ALE ADDR
WAIT STATE
GENERATOR AD0-
AD15
A16-A19

8286
TRAN-
ADDR/DATA CEIVER
DATA

RAM 2142 PERI-


2716
PHERAL
PROM
Bus Timing
The 8086/8088 microprocessors use the memory and I/O in periods
called bus cycles.
Each bus cycle consists of 4 clock cycles.
Thus for 8086 running at 5MHz it would take 800ns for a complete
bus cycle.
Each read or write operation take 1 bus cycles.

6
Read Timing
During T 1
:
•The address is placed on the
Address/Data bus.
•Control signals M/ IO , ALE and
DT/ R specify memory or I/O,
latch the address onto the
address bus and set the direction
of data transfer on data bus.

7
Read Timing
During T 2
:
•8086 issues the RD or WR
signal, DEN , and, for a write,
the data.
•DEN enables the
memory or I/O device
to receive the data for
writes and the 8086 to
receive the data for
reads.

8
During T 3 :
•This cycle is provided to allow memory to access data.
•READY is sampled at the end of T 2 .
•If low, T 3 becomes a wait state.
•Otherwise, the data bus is sampled at the end of T 3
.

9
During T 4 :
•All bus signals are deactivated, in preparation for next bus
cycle.
•Data is sampled for reads, writes occur for writes. 10
Write Timing

Convert this simple timeline to include all the necessary pins


Do as an EXERCISE !
11
Minimum Mode Interface
• Address/Data bus: 20 bits vs 8 bits
multiplexed
 • Status signals: A16-A19 multiplexed with
status signals S3-S6 respectively
 – S3 and S4 together form a 2 bit
binary code that identifies which of the
internal segment registers was used to
generate the physical address that was
output on the address bus during the
current bus cycle.
 – S5 is the logic level of the internal
interrupt enable flag, s6 is always logic 0.
Maximum mode unique
signals
Maximum-mode interface circuit
diagram (8086)
Maximum Mode 8086 System

Continued…
Maximum Mode Interface
 For multiprocessor environment
 • 8288 Bus Controller is used for bus
control
 • WR¯,IO/M¯,DT/R¯,DEN¯,ALE, INTA¯ signals
 are not available
 • Instead:
 – MRDC¯ (memory read command)
 – MWRT¯ (memory write command)
 – AMWC¯ (advanced memory write
command)
 – IORC¯ (I/O read command)
 – IOWC¯ (I/O write command)
 – AIOWC¯ (Advanced I/O write command)
 – INTA¯ (interrupt acknowledge)
Status Bits
They indicate the function of the
current bus cycle. They are
normally decoded by the 8288
bus controller
– The signals shown above are produced by
8288
depending on the state of S0, S1 and S2.
 • DEN, DT/R¯ and ALE signals are the same as

minimum-mode systems
 • LOCK¯: when =0, prevents other processors

from using the bus


 • QS0 and QS1 (queue status signals) : informs
about the status of the queue
 • RQ¯/GT ¯0 and RQ¯/GT ¯1 are used instead
of
HOLD and HLDA lines in a multiprocessor
environment as request/grant lines.
Memory Read timing in Maximum
Mode

Here MRDC* signal is


used instead of RD* as
in case of Minimum
Mode S0* to S2* are
active and are used to
generate control signal.
Read Cycle of the 8086 - maximum
mode

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