Operating Systems:

Internals and Design Principles, 6/E

William Stallings

Chapter 8
Virtual Memory – Part I
[Concepts + H/W Role]

Dave Bremer
Otago Polytechnic, N.Z.
©2008, Prentice Hall
*Lecture slides are modified by Dr. Ahmed Salah *
 GENERAL NOTE
Hidden Slides are Extra Knowledge
Not Included in Exams
 Roadmap
KNOW HOW the Operating System do its Main Jobs?

Solve competition on…

Shared
Memory CPU Resourc
e

Physical Virtual Single Critical

Multi CPU Deadlocks
Mem Mem CPU Sections
(CH.10) (CH.6)
(CH.7) (CH.8) (CH.9) (CH.5)
 Basic Memory Requirements
Logical Mem
Process X
1. Relocation
2. Protection
3. Sharing Any Loc.

4. Logical organisation
5. Physical organisation
RAM
 Partitioning
Fixed Partitioning: Dynamic Partitioning:
Split RAM into equal-size RAM is contiguous space
(+): (+):
1. Simple 1. No internal fragmentation
2. Little OS overheads 2. Efficient use of RAM
(-): 3. No limits on # processes
1. ProcSize > Part. 🡺Overlays (-):
2. Internal fragmentation 1. External fragmentation
3. Fixed # processes 2. Compaction

Placement: Placement:
Best Fit is Worst
• Doesn’t matter • Matter
• First, Next, Best, Worst fit...
 Address Translation
Fixed/Dynamic Address Translation:
OS
• Simple
• OS: set registers MMU
• MMU: perform translation (add, check)
 Paging
Paging: What’s the required info to be stored in table?
Logical of Process A RAM

Page#M-1 N-1

. N-2
.
. A
.
Process
.
Page#1 .

Page#0 2

PAGES 1

FRAMES
 Paging
• Extension of fixed partitioning

• Partition memory into small equal fixed-size chunks and

divide each process into the same size chunks

• The chunks of a process are called pages

• The chunks of memory are called frames
 Paging
• OS maintains:
1. page table for each process
• Contains the frame location for each page in process

2. Free Frame List

• A list of currently free frames in RAM
 4
5
Example 6

A.0
A.1
A.2
A.3
D.0
B.0
D.1
B.1
D.2
B.2
C.0
C.1
C.2
C.3
D.3
D.4
 Paging
• Advantages:
– No external fragmentation
– Reduce internal fragmentation
• Disadvantages
– Side-effect on the modular programming
 Address Translation (Ex)
Logical of Process A Logical Address RAM
P# (3 bits) Offset (11 bits)
Page#7 2 KB 15
Process A: Page Table
. 2 KB 14
. Page# Frame #
. 0 14 .
.
1 2
Page#1 .
.
Page#0 .
. 2 KB 2

PAGES 7 0
2 KB 1
Logical Address Physical Address
2 KB 0
0 KB 28 KB
Memory address consist
2 KB 4 KB
1. page number FRAMES
3 KB 2. offset within the page 5 KB
15 KB ?? KB
 Address Translation
Paging: ProcX Address Translation
Split RAM into frames A.0
A.1
Split process into pages A.2 A.2
(+): A.3
ProcX
1. No external fr. Page Table
A.0 F#
2. Small internal fr.
(-): 6
9
1. Affect modularity A.1
2

Placement: 13

• Doesn’t matter A.3

 Example
Given:
• Page Size = 1 KB
• Logical Address = 1502 (0000,0101,1101,1110)2
• Page table of Process A:
Page # 0 1 2
Frame # 5 6 17

Required
• Calculate corresponding physical address?
 Agenda
• Concepts
1. Virtual vs Physical PART I
2. Locality
3. Thrashing
• H/W Roles
– Virtual Paging
– Multilevel Paging
• Questions PART II
 Learning Outcomes

• Explain the workings of a system with virtual memory management.

• Describe the hardware and control structures that support virtual
memory
• Summarize the principles of virtual memory as applied to paging.
• Discuss the concept of thrashing in terms of the reasons it occurs
 References
• Chapter 8
– Section 8.1 (Concepts + H/W Roles)

• Stanford CS140
– Lec.5 Virtual Memory (H/W)

• Berkeley CS162
– Lec.13 Address Translation + Caching
 THE BASICS: Address/Address Space
Address
Space:

Addres 2k
s:
“things”
“Things” here
usually
k means “bytes” (8
bits bits)
• What is 210 bytes (where a byte is abbreviated as “B”)?
– 210 B = 1024B = 1 KB (for memory, 1K = 1024, not 1000)
• How many bits to address each byte of 4KB page?
– 4KB = 4×1KB = 4× 210= 212⇒ 12 bits
• How much memory can be addressed with 20 bits? 32 bits? 64 bits?
– Use 2k
Do we need to bring all pages?
 Last Lecture Example
What do we need
to add here? A.0
A.1
A.2
A.3
D.0
B.0
D.1
B.1
D.2
B.2
C.0
C.1
C.2
C.3
D.3
D.4
 Concepts

[1] Physical vs. Virtual Memory

[2] Principle of Locality

[3] Thrashing
 Concepts
[1] Physical vs. Virtual Memory
• Definition:
– Physical memory
• Main memory, the actual RAM

– Virtual memory
• Memory on disk
• Allows for effective multiprogramming and relieves the user of tight
constraints of main memory
 Concepts
[1] Physical vs. Virtual Memory
• Requirements:
1. Memory references are logical addresses dynamically
translated into physical addresses at run time
2. A process may be broken up into pieces that do not need to
located contiguously in main memory
 Concepts
[1] Physical vs. Virtual Memory
• Steps:
1. OS brings into main memory a few pieces of the program
[called Resident set]
2. An interrupt is generated when an address is needed that is
not in main memory
3. OS places the process in a blocking state
 Concepts
[1] Physical vs. Virtual Memory
• Steps:
4. Piece of process that contains the logical address is brought
into main memory
• OS issues a disk I/O Read request
• Another process is dispatched to run while the disk I/O takes place
• An interrupt is issued when disk I/O complete which causes the OS to
place the affected process in the Ready state
Steps in Handling a Page Fault

What’s
Process
Page
Fault State here?
Blocked

What’s What if
Process Mem/Process
State here? Size is Full?
Ready victim
Swap out a victim
 Concepts
[1] Physical vs. Virtual Memory
• Advantages:
1. More processes may be maintained in main memory
• Only load in some of the pieces of each process
• With so many processes in main memory, it is very likely a
process will be in the Ready state at any particular time

2. A process may be larger than all of RAM size

 Concepts
[2] Principle of Locality
• Definition:
– Program and data references within a process tend to cluster
– Only a few pieces of a process will be needed over a short
period of time
 [2] Principle of Locality

• As a program executes it transitions through a sequence of “working sets”

consisting of varying sized subsets of the address space
Addre
ss

Tim
e
 Concepts
[2] Principle of Locality
• Types:
• Temporal Locality (Locality in Time):
– Keep recently accessed data items closer to processor
• Spatial Locality (Locality in Space):
– Move contiguous blocks to the upper levels
Lower Level
To Processor Upper Level Memory
Memory
Blk X
From Processor Blk Y
 Concepts
[2] Principle of Locality
• Advantages:
– It is possible to make intelligent guesses about which
pieces will be needed in the future
– This suggests that virtual memory may work efficiently
 [2] Principle of Locality
• Program Memory Access
Patterns have temporal and
spatial locality
– Group of Pages accessed along a
given time slice called the “Working
Set”
– Working Set defines minimum
number of pages needed for
process to behave well
• Not enough memory for Working
Set ⇒Thrashing
– Better to swap out process?
 Concepts
[3] Thrashing
• Definition:
• A state in which the system spends most of its time swapping
pieces rather than executing instructions.
 Concepts
[3] Thrashing
• Solution:
• To avoid this, the OS tries to guess which pieces are least likely to
be used in the near future.
• The guess is based on recent history
 Agenda
• Concepts
1. Virtual vs Physical PART I
2. Locality
3. Thrashing
• H/W Roles
– Virtual Paging
– Multilevel Paging
• Intel MMU PART II
• Questions
 Different Roles

1. Hardware (H/W) must support paging and segmentation

2. OS must be able to manage the movement of pages
and/or segments between secondary memory and RAM
 Virtual Paging
• Each process has its own page table
• Each page table entry contains the frame number of the
corresponding page in main memory
• Two extra bits are needed to indicate:
1. Present bit: whether the page is in main memory or not
2. Modified bit: whether the contents of the page has been
altered since it was last loaded
 Virtual Paging

•P (present bit): indicates whether the corresponding page is

present in RAM or not.
Who•Mset the Present Bit? Who check it? OS. H/W (MMU)
(modified bit): indicates whether the contents of the
Whocorresponding page have
set the Modified Bit? been
Whoaltered
check since
it? theH/W
page was last
(MMU). OS
loaded
 Agenda
• Concepts
1. Virtual vs Physical PART I
2. Locality
3. Thrashing
• H/W Roles
– Virtual Paging
– Multilevel Paging
• Questions PART II
 Virtual Paging
• 3 Problems:
1. Sparse VM + Large Page Table!
2. Page table grows in RAM!
• Proportional to virtual memory/process
3. # references to RAM per program reference!!
• 1 Issue:
– Page Size
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
– What if page/frame size is small?
• (+) small internal fragmentation
• (-) Page table becomes big
• (-) Not all pages used all the time

– What if address space is sparse?

• E.g. on UNIX, code starts at 0, stack starts at (231-1).
• With 1K pages, need 2 million page-table entries!
 Pr1: Sparse VM + Large Page
Table!
Virtual memory in
UNUX
stack
How many entries in page table?

Are they all used?

heap
2 GB

data

code

1 KB
10/12/1 Kubiatowicz CS162 ©UCB Fall Lec 13.45
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
• Solution:
– Page table is divided into small pieces (each piece fits in a frame)
– Table pieces are also stored in virtual memory
– When a process is running, part of its page table is in RAM
 Pr1: Sparse VM + Large Page Table!
[Sol]
Virtual memory Page Physical memory
1111view Tables view
1111 stack (level
11
2)
stack 1110
Single table should fit
1111 1110
0000
1 0000
10
1100 Page Table 1110
(level 1) 0
0000 stack
111
110
in 1 frame
null
01
11 1011
null
1
101 null 10
00
1000
heap 100
🡺
1011
1000 011 null 0
0
0000
010 01 heap 0111
001 null 0111
000 11 1 0000

data
Min Beside
# Levels subject 00 0110
0111
1
10 0
data
0101
0000
0100 This one 0110
0
0000
to Max # entries per 01
11
0101
0010
code
page2 1
1
0001
# code 00
10
0000
0000
table (to fit inOnly
1 load
frame)
01
0101
0010
0
0
0000
0000
0000
page1 offs
# et these tables
0001
1
10/12/1 Kubiatowicz CS162 ©UCB00Fall Lec 13.47
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
• Example: 32-bit CPU
• Given:
• RAM size = 4 GB
• Virtual size / process = 4 GB
• Page size = 4 KB
• Questions: Page Table Size & Storage
• How many entries in page table?
• What’s the size of each entry (in Bytes)?
• What’s the total size of the page table?
• How we store it?
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
• Example: 32-bit CPU
• Answers:
• How many entries in page table?
= Virtual Size / Page Size = 4 GB / 4 KB = 1 M
• What’s the size of each entry (in bytes)?
Since # frames = 4 GB / 4 KB = 1 M = 220
Need 20 bit for Frame# + 2 bits (Present + Modified)
22 bits can be stored in integer data type (32 bit)
• What’s the total size of the page table?=1M*4B= 4MB
• How we store it? In separate frames of RAM
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
• Example: 32-bit CPU (cont.)
• Questions: #Levels & Address Translation
• How many bits for the offset & page#?
• How many bits in each level paging?
• What’s the min # levels for page tables?
• Where we store the address of 1st level table (directory)?
• How is the address translation done?
 SOLUTION – PART II (#Levels & Address Translation)
• How many bits for the offset & page#?
• How many bits in each level paging?
• What’s the min # levels for page tables?
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
• Example: 32-bit CPU (cont.)
• Answers:
• How many bits for the offset? 🡺Page size = 4 KB = 212 🡺 Offset = 12 bits
• How many bits in each level paging?
🡺 Max #entries/table to fit in 1 page = PageSize / EntrySize = 4 KB / 4 B = 210
🡺 10 bits for each
• What’s the min # levels for page tables?
🡺 Since Page# is 20 bits 🡺 at least 2 levels is required (each with 10 bits)
• Where we store the address of 1st level table (directory)?
🡺 In base register
 Two-level page table (32-bit 20 12 bits
CPU)
10 10
Physica bits
Physical
Frame# Offset
Virtua Virtua 12 l
Virtual bits
l lbits bits
P1 P2 Offset Addres
Addres index index s:
s: 4KB

PageTable V
0
Ptr 1
0
…
1
1
0
…
4 bytes
• Tree of Page Tables
• Tables fixed size (1024 entries)
– On context-switch: save single
PageTablePtr register
• Valid bits on Page Table Entries
– Don’t need every 2nd-level table
– Even when exist, 2nd-level tables can 4 bytes
reside on disk if not in use
10/12/1 Kubiatowicz CS162 ©UCB Fall Lec 13.53
 Virtual Paging
Pr1: Sparse VM + Large Page Table!
• Example: Address Translation
 Agenda
• Concepts
1. Virtual vs Physical PART I
2. Locality
3. Thrashing
• H/W Roles
– Virtual Paging
– Multilevel Paging
• Questions PART II
 Questions
FIRST: Textbook
• Virtual Paging 8.1
• Multilevel Paging 8.10
• Inverted Page Table 8.3
Question
Question
 Solutions
8.1:
a) Split binary address into virtual page number and offset; use VPN as
index into page table; extract page frame number; concatenate offset to
get physical memory address
b)
(i) 1052 = 1024 + 28 maps to VPN 1 in PFN 7, (7 × 1024+28 = 7196)
(ii) 2221 = 2 × 1024 + 173 maps to VPN 2, page fault
(iii) 5499 = 5 × 1024 + 379 maps to VPN 5 in PFN 0, (0 × 1024+379 = 379)
Question
 Solutions
8.10:
Since each page table entry is 4 bytes and each page contains 4 Kbytes,
then a one-page page table would point to 1024 = 2 10 pages, addressing
a total of 210 * 212 = 222 bytes.
The address space however is 264 bytes.
Adding a second layer of page tables, the top page table would point to 2 10
page tables, addressing a total of 232 bytes.
Continuing this process,Depth_Address Space__1_222 bytes__2_232
bytes__3_242 bytes__4_252 bytes__5_262 bytes__6_272 bytes (> 264 B)
We can see that 5 levels do not address the full 64 bit address space, so a
6th level is required. But only 2 bits of the 6th level are required, not the
entire 10 bits.
So instead of requiring your virtual addresses be 72 bits long, you could
ignore all but the 2 lowest order bits of the 6th level. This would give you
a 64 bit address. Top level page table then would have only 4 entries.
 Question
• In a system using a virtual paging:
– page size is 4 MB
– program virtual memory size is 4 GB
– physical memory size is 4 GB.
– It’s desired to limit the page table size to one page. Answer
the following questions:
1. What’s the size (in bytes) of a page table entry to support
virtual paging?
2. What’s the min number of levels for the page tables?
3. If an inverted page table is used, how many entries in it?
4. If the max number of processes is 1024, what’s the
number of bits of each entry in this inverted page table?
 Solution
• What’s the size (in bytes) of a page table entry to support virtual paging? 10
+ 2 (P & M) = 12 bit
• What’s the min number of levels for the page tables? 1
• If an inverted page table is used, how many entries in it? 210 = 1 K
• If the max number of processes is 1024, what’s the number of bits of each
entry in this inverted page table? 10(P#) + 10(process ID) + 10(chain
index) = 30 bits
 Question
• Consider a paged logical address space (composed of 32 pages
of 2 Kbytes each) mapped into a 1-Mbyte physical memory
space.
1. What is the format of the logical address?
2. What is the length and width of the page table (disregarding the “access
rights” bits)?
3. What is the effect on the page table if the physical memory space is
reduced by half?
 Solution
• What is the format of the logical address?
– No of pages=32 = 25 🡺 Page number = 5 bit
– Page size = 2 Kbyte = 211 🡺 offset=11 bit
5 bit 11 bit
Page# Offset
 Solution
• What is the length and width of the page table (disregarding
the “access rights” bits)?
– Page table length = # entries in table = 32
– Page table width = entry size, which consists of frame number
– Since physical memory = 1 MB 🡺 # frames = 1 MB / 2 KB = 29 frames 🡺
number of bits for frame number = 9 bits
– So, page table width= 9 bits
 Solution
• What is the effect on the page table if the physical memory
space is reduced by half?
– If the physical memory reduced by half 🡺 number of frames is reduced by
half = 29 / 2 = 28
– So, page table width will be reduced to 8 bits
 Questions
• Midterm'09 Ver. II: Q.1
 Solution
• Midterm'09 Ver. II: Q.1
virtual address = 32 bits
page size = 1 K Byte 🡺 offset = 10 bits
So, virtual address will look like this:

Page # (22 bits) Offset (10 bits)

 Solution
Since it’s desired to limit page table size to 1 page
And each page table entry = 16 bits = 2 bytes
Then # of page table entries
= size of 1 page / size of 1 entry
= 1024 / 2 = 512 entries = 29
So, MAX page # for each table = 9 bits
 Solution
As a result, the 22 bits of page # should be divided
to levels so that # of bits for each level can’t
exceed 9 bits (i.e. in order to access max 512
entries of the table)
So the virtual address can be divided as either:
L1 (4 bits) L2 (9 bits) L3 (9 bits) Offset (10 bits)
OR
L1 (9 bits) L2 (9 bits) L3 (4 bits) Offset (10 bits)
 Solution
• In Strategy 1:
– # of tables at L1 = 1 table
– # of tables at L2 = 24 tables = 16 tables
– # of tables at L3 = 16 * 29 tables = 8,192 tables
– Total # of tables = 1 + 16 + 8,192 = 8,209 tables
– Since each table takes 1 page, number of pages for
tables = 8,209 pages
 Solution
• In Strategy 2:
– # of tables at L1 = 1 table
– # of tables at L2 = 29 tables = 512 tables
– # of tables at L3 = 512 * 29 tables = 262,144
– Total # of tables = 1 + 512 + 262,144 = 262,657
– Since each table takes 1 page, number of pages for
tables = 262,657 pages
• As a result, STRATEGY 1 consumes the least
number of pages