CHAPTER 7

CPU AND MEMORY

The Architecture of Computer

Hardware,
Systems Software & Networking:
An Information Technology Approach
6th Edition, Irv Englander and Wilson Wong

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OVERVIEW
Components of the CPU
Registers
Memory Unit
Fetch-Execute Cycle
Instructions

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CPU AND MEMORY
Every instruction executed by the CPU
requires memory access
Primary memory holds program
instructions and data
Secondary storage is used for long term
storage
 Data is moved from secondary storage to
primary memory for CPU execution

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CPU
MAJOR COMPONENTS
ALU (arithmetic logic unit)
 Performs calculations and comparisons
CU (control unit)
 Performs fetch/execute cycle
 Runs program instructions and issues commands
to the ALU
 Moves data to and from CPU registers and other
hardware components
 Subcomponents
 Memory management unit
supervises fetching instructions and data from
memory
 I/O Interface: sometimes combined with the
4
memory management unit as the Bus Interface
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SYSTEM BLOCK DIAGRAM

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THE LITTLE MAN COMPUTER

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CONCEPT OF REGISTERS
Small, permanent storage locations
within the CPU used for a particular
purpose
Manipulated directly by the Control Unit
Wired for specific function
Size in bits or bytes (not in MB like
memory)
Can hold data, an address, or an
instruction
How many registers does the LMC have?
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REGISTERS
 Use of Registers
 Scratchpad for currently executing program
 Holds data needed quickly or frequently
 Stores information about status of CPU and currently
executing program
 Address of next program instruction
 Signals from external devices
 General Purpose Registers
 User-visible or program-visible registers
 Hold intermediate results or data values, e.g., loop
counters
 Equivalent to LMC’s calculator
 Typically several dozen in current CPUs
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SPECIAL-PURPOSE REGISTERS
Program Counter Register (PC)
 Also called instruction pointer (IP)
Instruction Register (IR)
 Stores instruction fetched from memory
Memory Address Register (MAR)
Memory Data Register (MDR)
Status Registers
 Status of CPU and currently executing
program
 Flags (one bit Boolean variable) to track
conditions like arithmetic carry and over
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REGISTER OPERATIONS
Stores values from other locations
(registers and memory)
Addition and subtraction
Shift or rotate data
Test contents for conditions such as zero
or positive

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OPERATION OF MEMORY
Each memory location has a unique
address
Address from an instruction is copied to
the MAR, which finds the location in
memory
CPU determines if it is a store or retrieval
Transfer takes place between the MDR
and memory
MDR is a two way register
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RELATIONSHIP BETWEEN
MAR, MDR AND MEMORY
Addres Data
s

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MAR-MDR EXAMPLE

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VISUAL ANALOGY OF MEMORY

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INDIVIDUAL MEMORY CELL

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MEMORY CAPACITY AND ADDRESSING
LIMITATIONS
Determined by two factors
1. Number of bits in the MAR
 LMC = 100 (00 to 99)
 2K where K = width of the register in bits
2. Size of the address portion of the instruction
 4 bits allows 16 locations
 8 bits allows 256 locations
 32 bits allows 4,294,967,296 or 4 GB
 64 bits allows 16 EB (exabytes)

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RAM
RANDOM ACCESS MEMORY
DRAM (Dynamic RAM)
 Most common, cheap, less electrical power,
less heat, smaller space
 Volatile: must be refreshed (recharged with
power) 1000’s of times each second
SRAM (static RAM)
 Faster and more expensive than DRAM
 Volatile
 Small amounts are often used in cache
memory for high-speed memory access
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NONVOLATILE MEMORY
ROM
 Read-only Memory
 Holds software that is not expected to change
over the life of the system such as firmware
used for the system BIOS
Flash Memory
 Inexpensive nonvolatile secondary storage
 Useful for nonvolatile portable computer
storage, digital cameras, tablets, smartphones
 Slower rewrite time compared to RAM

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FETCH-EXECUTE CYCLE
Two-cycle process because both
instructions and data are in memory
Fetch
 Decode or find instruction, load from memory
into register and signal ALU
Execute
 Performs operation that instruction requires
 Move/transform data

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LMC VS. CPU
FETCH AND EXECUTE CYCLE

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LOAD FETCH/EXECUTE CYCLE
1. PC  MAR Transfer the address from
the PC to the MAR
2. MDR  IR Transfer the instruction to
the IR
3. IR[address]  Address portion of the
MAR instruction loaded in MAR
4. MDR  A Actual data copied into the
accumulator
5. PC + 1  PC Program Counter
incremented
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STORE FETCH/EXECUTE CYCLE
1. PC  MAR Transfer the address from
the PC to the MAR
2. MDR  IR Transfer the instruction to
the IR
3. IR[address]  Address portion of the
MAR instruction loaded in MAR
4. A  MDR* Accumulator copies data
into MDR
5. PC + 1  PC Program Counter
incremented
*Notice how Step #4 differs for LOAD and STORE
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ADD FETCH/EXECUTE CYCLE
1. PC  MAR Transfer the address from
the PC to the MAR
2. MDR  IR Transfer the instruction to
the IR
3. IR[address]  Address portion of the
MAR instruction loaded in MAR
4. A + MDR  A Contents of MDR added to
contents of accumulator
5. PC + 1  PC Program Counter
incremented

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LMC FETCH/EXECUTE
SUBTRACT INPUT BRANCH HALT
PC  MAR PC  MAR PC  MAR PC  MAR
MDR  IR MDR  IR MDR  IR MDR  IR
IR[addr]  MAR IOR  A IR[addr] 
A – MDR  A PC + 1  PC PC
PC + 1  PC

OUTPUT BRANCH on Condition

PC  MAR PC  MAR
MDR  IR MDR  IR
A  IOR If condition true: IR[addr] 
PC + 1  PC PC
If condition false: PC + 1 
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CLASSIFICATION OF INSTRUCTIONS
 Data Movement (load, store)
 Most common, greatest flexibility
 Involve memory and registers
 What’s the size of a word? 16, 32, or 64 bits?
 Arithmetic
 Operators + - / * ^
 Integers and floating point
 Boolean Logic
 Often includes at least AND, XOR, and NOT
 Single operand manipulation instructions
 Negating, decrementing, incrementing, set to 0

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MORE INSTRUCTION
CLASSIFICATIONS
Bit manipulation instructions
 Flags to test for conditions
Shift and rotate
Program control
Stack instructions
Multiple data instructions
I/O and machine control

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REGISTER SHIFTS AND ROTATES

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PROGRAM CONTROL INSTRUCTIONS
Program
control
 Jump and
branch
 Subroutine
call
and return

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STACK INSTRUCTIONS
 Stack instructions
 LIFO method for organizing information
 Items removed in the reverse order from how they are
added

Push Pop

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FIXED LOCATION SUBROUTINE
RETURN ADDRESS STORAGE: OOPS!

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STACK SUBROUTINE RETURN ADDRESS STORAGE

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BLOCK OF MEMORY AS A STACK

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MULTIPLE DATA INSTRUCTIONS
 Perform a single operation on multiple pieces of
data simultaneously
 SIMD: Single Instruction, Multiple Data
 Commonly used in multimedia, vector and array
processing applications

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INSTRUCTION ELEMENTS
OPCODE: task
Source OPERAND(s)
Addresses
Result OPERAND
 Location of data (register, memory)
 Explicit: included in instruction
 Implicit: default assumed

Source Result
OPCODE OPERAND OPERAND

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INSTRUCTION FORMAT
Machine-specific template that specifies
 Length of the op code
 Number of operands
 Length of operands

Simple 32-
bit
Instruction
Format

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INSTRUCTIONS
 Instruction
 Direction given to a computer
 Causes electrical signals to be sent through specific
circuits for processing
 Instruction set
 Design defines functions performed by the processor
 Differentiates computer architecture by the
 Number of instructions
 Complexity of operations performed by individual
instructions
 Data types supported
 Format (layout, fixed vs. variable length)
 Use of registers
 Addressing (size, modes)
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INSTRUCTION WORD SIZE
Fixed vs. variable size
 Pipelining has mostly eliminated variable
instruction size architectures
Most current architectures use 32-bit or
64-bit words
Addressing Modes
 Direct
 Mode used by the LMC
 Register Deferred
 Also immediate, indirect, indexed
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 INSTRUCTION FORMAT EXAMPLES

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SONS
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