The Arm Cortex-M4

Processor Architecture
Syllabus
This module will cover the following topics

• What is the Arm architecture

• Arm processor families
• The Arm Cortex-M series
• The Arm Cortex-M4 processor
• Arm Cortex-M4 registers

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Arm architectures and processors
A family of RISC-based processor architectures

Architecture well-known for its power efficiency

Widely used in mobile and IoT devices, e.g., smartphones, connected cars, wearables

Designed and licensed by Arm Holdings to a wide ecosystem of partners

Arm does not manufacture, but it licenses designs to semiconductor companies, who add their own
intellectual property (IP) on top of Arm’s IP

Arm also offers IP other than for processors, such as physical IPs, interconnect IPs, graphics cores, and
development tools.

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Arm processor families
• Cortex-A series (application) Cortex-A73
Cortex-A72
Cortex-A57
• High performance processors capable of full OS support Cortex-A53
Cortex-A35
Cortex-A32
• Applications include smartphones, digital TVs, and smart books. Cortex-A17
Cortex-A15
Cortex-A9
Cortex-A
• Cortex-R series (real-time) Cortex-A8
Cortex-A7
Cortex-A5
• High performance and reliability for real-time applications Cortex-R8
Cortex-R7
• Applications include automotive braking systems and powertrains. Cortex-R5
Cortex-R4
Cortex-R

• Cortex-M series (microcontroller)

Cortex-M7
Cortex-M4
Cortex-M3
Cortex-M0+ Cortex-M
• Cost-sensitive solutions for deterministic microcontroller applications Cortex-M0

• Applications include microcontrollers and smart sensors.

SC000
SecurCore
SC300
Arm11

• SecurCore series for high security applications Arm9

Arm7
Classic

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Arm processors vs. Arm architectures
Arm architecture Arm processor
• Describes the details of the instruction set, • Developed using one of the Arm architectures
programmer’s model, exception model, and • More implementation details, such as timing
memory map information
• Documented in the Architecture Reference • Documented in the processor’s Technical
Manual Reference Manual

Armv4/v4T Armv5/v4E Armv6 Armv7 Armv8 Architecture

Architecture Architecture Architecture Architecture Armv7-A Armv8-A
e.g., Cortex-A9 e.g., Cortex-
A53
Armv7-R Cortex-A57
e.g., Cortex-R4 Armv8-R

Arm v6-M Armv7-M

e.g., Cortex-M0, M1 e.g., Cortex-M4

e.g., Arm7TDMI e.g., Arm9926EJ-S e.g., Arm1136

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How to design an Arm-based SoC
IP libraries SoC
Cortex-A9 Cortex-R5 Cortex-M4 Arm
ROM RAM
processor
Arm7 Arm9 Arm11
System bus Arm-based
DRAM ctrl FLASH ctrl SRAM ctrl SoC
Peripherals
AXI bus AHB bus APB bus

GPIO I/O blocks Timer

External Interface

Licensable IPs SoC Design Chip

Manufacture
• Select a set of IP cores from Arm and/or other third-party IP vendors.
• Integrate IP cores into a single chip design.
• Give design to semiconductor foundries for chip fabrication.

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The Arm Cortex-M series
Cortex-M0, M0+, M3, M4, M7

• Energy-efficiency
• Lower energy cost, longer battery life
• Smaller code
• Lower silicon costs
• Ease of use
• Faster software development and reuse
• Embedded applications
• Smart metering, human interface devices, automotive and industrial
control systems, consumer products (white goods, home automation,
wearables, etc.), and medical instrumentation

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The Arm Cortex-M series
Processor Arm Core Thumb® Thumb®-2 Hardware Hardware Saturated DSP Floating
Architecture Architecture Multiply Divide Math Extensions Point

Cortex-M0 Armv6-M Von Neumann Most Subset 1 or 32 cycle No No No No

Cortex-M0+ Armv6-M Von Neumann Most Subset 1 or 32 cycle No No No No

Cortex-M3 Armv7-M Harvard Entire Entire 1 cycle Yes Yes No No

Cortex-M4 Armv7E-M Harvard Entire Entire 1 cycle Yes Yes Yes Optional

Cortex-M7 Armv7E-M
Harvard Entire Entire 1 cycle Yes Yes Yes Optional

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The Cortex-M4 processor
Overview

Design Performance Power consumption

32-bit reduced instruction set 1.25DMIPS/MHz (Dhrystone Million Longer battery life; especially critical
computing (RISC) processor Instructions Per Second/MHz) in the in mobile and IoT products
Harvard architecture – separate data order of µWatts/MHz
and instruction buses Large variety of highly efficient signal
processing features

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The Cortex-M4 processor
Features
• Computation
• Includes the entire Thumb-1 (16-bit) and Thumb-2 (16/32-bit) instruction sets
• 3-stage + branch speculation pipeline

• Supported interrupts
• Non-maskable interrupt (NMI) + 1 to 240 physical interrupts
• 8 to 256 interrupt priority levels

• Enhanced determinism
• The critical tasks and interrupt routines can be served quickly in a known number of cycles
• Configurable system timer (SysTick) to trigger periodic interrupts

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The Cortex-M4 processor
Features

• Sleep modes
• Up to 240 wake-up interrupts
• Integrated wait for interrupt (WFI) and wait for event (WFE) instructions, and sleep on exit capabilities
• Sleep & deep sleep signals
• Optional retention mode with Arm Power Management Kit

• Debug
• Optional JTAG & serial-wire debug (SWD) ports
• Up to eight breakpoints and four watchpoints

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The Cortex-M4 processor
Features

• Enhanced instructions
• Hardware divide (2–12 cycles)
• Single-cycle 16, 32-bit multiply-with-accumulate (MAC) instructions, single-cycle dual 16-bit MAC
• Optimizes 8, 16-bit single instruction, multiple data (SIMD) arithmetic
• Saturating arithmetic and optional floating-point unit (FPU)

• Memory protection unit (MPU)

• Optional eight-region MPU with sub regions and background regions

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The Cortex-M4 processor
Features
The Cortex-M4 processor is designed to meet the challenges of low dynamic power
constraints while retaining a light footprint.
• 180ULL ultra low power process: 151µW/MHz
• 90LP low power process: 32.82µW/MHz
• 40LP low power process: 12.26µW/MHz

Arm Cortex-M4 Implementation Data

180ULL 90LP 40G

Process
(7-track, typical 1.8v, 25C) (7-track, typical 1.2v, 25C) (9-track, typical 0.9v, 25C)

Dynamic power 151µW/MHz 32.82µW/MHz 12.26µW/MHz

Floor planned area 0.44mm2 0.119mm2 0.028mm2

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Cortex-M4 block diagram
Arm Cortex-M4 Microprocessor

Optional FPU
Nested Vector Optional
Optional
Interrupt WIC
Interrupt Embedded
Controller Processor core
components (NVIC)
Trace Macrocell

Optional
Optional Memory Optional Serial
Debug
protection unit Wire Viewer
Access Port

Real-time
Optional Optional program
Flash Data
patch Data watchpoints tracing
tracing

Bus matrix
SRAM and
Code interface
peripheral interface

Memory interfaces
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Cortex-M4 block diagram
• Processor core
• Contains internal registers, the ALU, data path, and some control logic
• Registers include sixteen 32-bit registers for both general and special usage.

• Processor pipeline stages

• Three-stage pipeline: fetch, decode, and execution
• Some instructions may take multiple cycles to execute, in which case the pipeline will be stalled.
• Speculatively prefetches instructions from branch target addresses
• Up to two instructions can be fetched in one transfer (16-bit instructions).

Instruction 1 Fetch Decode Execute

Instruction 2 Fetch Decode Execute

Instruction 3 Fetch Decode Execute

Instruction 4 Fetch Decode Execute

Time
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Cortex-M4 block diagram
• NVIC
• Up to 240 interrupt request signals and an NMI
• Automatically handles nested interrupts, such as comparing priorities between interrupt requests and
the current priority level

• WIC
• For low-power applications, the microcontroller can enter sleep mode by shutting down most of the
components.
• When an interrupt request is detected, the WIC can inform the power management unit to power up
the system.

• MPU (optional)
• Used to protect memory content, e.g., make some memory regions read-only or preventing user
applications from accessing privileged application data

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Cortex-M4 block diagram

• Bus interconnect
• Allows data transfer to take place on different buses simultaneously
• Provides data transfer management, e.g., write buffer, bit-oriented operations (bit-band)
• May include bus bridges (e.g., AHB-to-APB bus bridge) to connect different buses into a network using
a single global memory space
• Includes the internal bus system, the data path in the processor core, and the AHB-Lite interface unit.

• Debug subsystem
• Handles debug control, program breakpoints, and data watchpoints
• When a debug event occurs, it can put the processor core in a halted state, so that developers can
analyze the status of the processor, including register values and flags, at a particular point.

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Arm Cortex-M4 processor registers
Processor registers
• The internal registers are used to store and process temporary data within the processor core.
• All registers are inside the processor core, so they can be accessed quickly.
• Load-store architecture
• To process memory data, they have to be first loaded from memory to registers, processed
inside the processor core using register data only, and then written back to memory if needed.

Cortex-M4 registers
• Register bank
• Sixteen 32-bit registers (thirteen are used for general-purpose)
• Special registers

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Arm Cortex-M4 processor registers
Register bank R0
R1
R2
R3
Low
R4 Registers

R5
General-purpose
R6
register
R7
R8
R9
R10 High
Registers
R11
R12 MSP
SP R13 (banked) Main SP

LR R14 PSP
PC R15 Process SP

Special registers Program Status Registers (PSR) x PSR APSR EPSR IPSR
PRIMASK Application Execution Interrupt
PSR PSR PSR
Interrupt mask register FAULTMASK
BASEPRI
Stack definition CONTROL

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Arm Cortex-M4 processor registers
Data Data
• R0–R12: General-purpose registers
• Low registers (R0–R7) can be accessed by any instruction. PUSH POP

• High registers (R8–R12) sometimes cannot be accessed, e.g., by some Low

Thumb (16-bit) instructions.
Stack Address

• R13: SP SP
High
• Records the current address of the stack PC

• Used for saving the context of a program while switching between tasks Heap
• Cortex-M4 has two SPs: Main SP, used in applications that require
privileged access, e.g., OS kernel, and Process SP, used in base-level
application code (when not running an exception handler)
Code

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Arm Cortex-M4 processor registers
Data Data

PUSH POP
• PC
• Records the address of the current instruction code Low

• Automatically incremented by four at each operation (for 32-bit instruction Stack Address
code), except branching operations
SP
• A branching operation, such as function calls, will change the PC to a High
specific address, while saving the current PC to the LR. PC
Heap

Code

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Arm Cortex-M4 processor registers

• R14: LR
• The LR is used to store the return address of a subroutine or a function call.
• The PC will load the value from LR after a function is finished.

Current PC Current LR
PC LR
1. Save current Main Main
PC to LR Program Program

Code region
code Load PC with the code

Code region
LR
address in LR to
return to the
2. Load PC with main program
the starting
address of the
subroutine subroutine
subroutine Current PC
PC

Call a subroutine Return from subroutine to main program

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Arm Cortex-M4 processor registers
• xPSR: Combined program status register (PSR)
• Provides information about program execution and ALU flags
• Application PSR (APSR) - contains condition code flags
• Interrupt PSR (IPSR) - contains Interrupt Service Routine (ISR) number of current exception activation
• Execution PSR (EPSR) - contains two overlapping fields (detailed next)

APSR N Z C V Q Reserved

IPSR Reserved ISR number

EPSR ICI/IT T Reserved ICI/IT

xPSR N Z C V Q ICI/IT T Reserved ICI/IT ISR number

bit31 bit24 bit16 bit8 bit0

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Arm Cortex-M4 processor registers
• APSR
• N: Negative flag: set to one if the result from the ALU is negative
• Z: Zero flag: set to one if the result from the ALU is zero
• C: Carry flag: set to one if an unsigned overflow occurs
• V: Overflow flag: set to one if a signed overflow occurs
• Q: Sticky saturation flag: set to one if saturation has occurred in saturating arithmetic instructions, or
overflow has occurred in certain multiply instructions

• IPSR
• Interrupt service routine (ISR) number: current executing ISR number

• EPSR
• T: Thumb state: always one since Cortex-M4 only supports the Thumb state
• IC/IT: Interrupt-Continuable Instruction (ICI) bit, IF-THEN instruction status bit

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Arm Cortex-M4 processor registers
• Exception mask registers • CONTROL: Special register
• 1-bit PRIASK - If set to one, blocks all interrupts • 1-bit stack definition
apart from NMI and the hard fault exception – Set to one to use the PSP
– Clear to zero to use the MSP
• 1-bit FAULTMASK - If set to one, will block all
the interrupts apart from NMI
• 1-bit BASEPRI - If set to one, will block all
interrupts of the same or lower level (only
allowing for interrupts with higher priorities)

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Coming next
Module Contents
Interrupts and Low Power • What are interrupts
Features • Exception handlers
• Timing analysis
• Program design with interrupts
Introduction to the Mbed • Mbed Overview
Platform • Mbed OS
• Mbed SW/HW Development Kit
• CMSIS
IoT Connectivity, Part I • Introduction to Bluetooth
• Bluetooth Low Energy
• ZigBee

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